ADMCF326BR Analog Devices Inc, ADMCF326BR Datasheet - Page 10

• Manufacturer Part Number: ADMCF326BR
• Description: IC DSP FLASH MOTOR CTRLR 28SOIC
• Manufacturer: Analog Devices Inc
• Series: Motor Controlr
• Type: Fixed Pointr

Specifications of ADMCF326BR

• Rohs Status: RoHS non-compliant
• Interface: Synchronous Serial Port (SSP)
• Clock Rate: 20MHz
• Non-volatile Memory: FLASH (12 kB), ROM (12kB)
• On-chip Ram: 2.5kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)

ADMCF326
FLASH MEMORY SUBSYSTEM
The ADMCF326 has 4K × 24-bit of user-programmable, non-
volatile flash memory. A flash programming utility is provided
with the development tools, which performs the basic device
programming operations: erase, program, and verify.
The flash memory array is partitioned into three asymmetrically
sized sectors of 256 words, 256 words, and 3584 words, labeled
Sector 0, Sector 1, and Sector 2, respectively. These sectors are
mapped into external program memory address space.
Four flash memory interface registers are connected to the DSP.
These 16-bit registers are mapped into the register area of data
memory space. They are named Flash Memory Control Register
(FMCR), Flash Memory Address Register (FMAR), Flash
Memory Data Register Low (FMDRL), and Flash Memory Data
Register High (FMDRH). These registers are diagrammed later in
this data sheet. They are used by the flash memory programming
utility. The user program may read these registers, but should not
modify them directly. The flash programming utility provides
a complete interface to the flash memory.
Special Flash Registers
The flash module has four nonvolatile 8-bit registers called Special
Flash Registers (SFRs) that are accessible independently of the
main flash array via the flash programming utility. These regis-
ters are for general-purpose, nonvolatile storage. When erased,
the Special Flash Registers contain all 0s. To read Special Flash
Registers from the user program, call the read_reg routine con-
tained in ROM. Refer to the ADMCF32x DSP Motor Controller
Developer’s Reference Manual for an example.
Boot-from-Flash Code
A security feature is available in the form of a code that, when set,
causes the processor to execute the program in flash memory upon
power-up or reset. In this mode, the flash programming utility
and debugger are unable to communicate with the ADMCF326.
Consequently, the contents of the flash memory can neither
be programmed nor read.
The boot-from-flash code may be set via the flash programming
utility, when the user’s program is thoroughly tested and loaded
into flash program memory at address 0x2200. The user’s program
must contain a mechanism for clearing the boot-from-flash code
if reprogramming the flash memory is desired. The only way
to clear boot-from-flash is from within the user program, by calling
the flash_init or auto_erase_reg routines that are included in
the ROM. The user program must be signaled in some way to call
the necessary routine to clear the boot-from-flash code. An example
would be to detect a high level on a PIO pin during start-up initial-
ization and then call the flash_init or auto_erase_routine. The
flash_init routine will erase the entire user program in flash
memory before clearing the boot-from-flash code, thus ensuring
the security of the user program. If security is not a concern, the
auto_erase_reg routine can be used to clear the boot-from-flash
code while leaving the user program intact.
Refer to the ADMCF32x DSP Motor Controller Developer’s Reference
Manual for further instructions and an example of using the
boot-from-flash code.
FLASH PROGRAM BOOT SEQUENCE
On power-up or reset, the processor begins instruction execu-
tion at address 0x0800 of internal program ROM. The ROM
–10–
monitor program that is located there checks the boot-from-
flash code. If that code is set, the processor jumps to location
0x2200 in external flash program memory, where it expects to
find the user’s application program.
If the boot-from-flash code is not set, the monitor attempts to
boot from an external device as described in the ADMCF32x
DSP Motor Controller Developer’s Reference Manual
SYSTEM INTERFACE
Figure 4 shows a basic system configuration for the ADMCF326
with an external crystal.
Clock Signals
The ADMCF326 can be clocked either by a crystal or a TTL-
compatible clock signal. For normal operation, the CLKIN
input cannot be halted, changed during operation, or operated
below the specified minimum frequency. If an external clock is
used, it should be a TTL-compatible signal running at half
the instruction rate. The signal is connected to the CLKIN pin
of the ADMCF326. In this mode, with an external clock signal,
the XTAL pin must be left unconnected. The ADMCF326 uses
an input clock with a frequency equal to half the instruction
rate; a 10 MHz input clock yields a 50 ns processor cycle (which
is equivalent to 20 MHz). Normally, instructions are executed
in a single processor cycle. All device timing is relative to the
internal instruction rate, which is indicated by the CLKOUT
signal when enabled.
Because the ADMCF326 includes an on-chip oscillator feedback
circuit, an external crystal may be used instead of a clock source, as
shown in Figure 4. The crystal should be connected across the
CLKIN and XTAL pins, with two capacitors as shown in Figure 4.
A parallel-resonant, fundamental frequency, microprocessor-grade
crystal should be used. A clock output signal (CLKOUT) is
generated by the processor at the processor’s cycle rate of twice
the input frequency.
Reset
The ADMCF326 DSP core and peripherals must be correctly
reset when the device is powered up to assure proper initialization.
The ADMCF326 contains an integrated power-on reset (POR)
circuit that provides a complete system reset on power-up and
power-down. The POR circuit monitors the voltage on the
ADMCF326 V
in reset while V
When this voltage is exceeded, the ADMCF326 is held in reset
for an additional 2
power-down, when the voltage on the V
V
RESET pin is actively pulled low at any time after power-up, a
complete hardware reset of the ADMCF326 is initiated.
RST
–V
HYST
Figure 4. Basic System Configuration
, the ADMCF326 will be reset. Also, if the external
DD
DD
pin and holds the DSP core and peripherals
is less than the threshold voltage level, V
16
CLKOUT
RESET
DSP clock cycles (t
ADMCF326
CLKIN
XTAL
10MHz
RST
22pF
22pF
DD
in Figure 5). On
pin falls below
REV. B
RST
.