Z8927320VSG Zilog, Z8927320VSG Datasheet
Z8927320VSG
Specifications of Z8927320VSG
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Z8927320VSG Summary of contents
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FEATURES Device Package Z89223 44-PLCC, 44-PQFP Z89273 44-PLCC Z89323 64-TQFP, 68-PLCC, 80-PQFP Z89373 64-TQFP, 68-PLCC, 80-PQFP Operating Range 5V ±10% • 0°C to 70°C Standard Temperature • –40°C to +85°C Extended Temperature DSP Core 16-Bit Fixed Point DSP, 24-Bit ALU ...
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... P1.0 or INT2 P1.1 or CLKOUT P1.2 or SDI P1.3 or SDO 8-Bit I/O P1 P1.5 or SCLK P1.6 or UI0 P1.7 or UI1 Port 2 P2.0 or INT0 P2.1 or INT1 P2.2 or TMO0 P2.3 or TMO1 8-Bit I/O P2.4 or WAIT P2.5 or UI2 P2.6 or TMO2 P2.7 P3.7–P3.4 4 Inputs 4 Outputs P3.3–P3.0 DS000202-DSP0599 ZiLOG ...
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... ZiLOG External Bus and External Registers. made to clarify naming conventions used in this specifica- tion. The external bus and external registers are external to Z893x3 External Register Internal Peripheral DS000202-DSP0599 16-Bit Digital Signal Processors with A/D Converter The following is the DSP core, and are used to access internal and external peripherals ...
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... Counter/Timer1 may use either of these pins as input. User Input (input). This pin is the input to UI2. Counter/Timer 2. Counter/Timer Output or User Output 0 (out- TMO0/UO0. put). Counter/Timer 0 and Counter/Timer 1 can be pro- grammed to provide output on this pin. When User Outputs vides the complement of Status Register bit 5. ZiLOG DS000202-DSP0599 ...
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... ZiLOG Counter/Timer Output or User Output 1 (out- TMO1/UO1. put). Counter/Timer 0 and Counter/Timer 1 can be pro- grammed to provide output on this pin. When User Outputs are enabled, and the Counter/Timer is disabled, this pin pro- vides the complement of Status Register bit 6. Counter/Timer 2 Output (output). This pin is the TMO2 ...
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... Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter PIN CONFIGURATIONS ED3/P0.3 ED4/P0 ED5/P0.5 ED6/P0.6 ED7/P0.7 ED8/P0.8 ED9/P0 ED10/P0.10 ED11/P0.11 Figure 3. 44-Pin PLCC Z89223/273 Pin Configuration 44-Pin 34 12 PLCC RESET LPF P2.2/TMO0/UO0 CLKO CLKI P2.4/WAIT DS P2.3/TMO1/UO1 EA2 EA1 EA0 DS000202-DSP0599 ZiLOG ...
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... ZiLOG Table 1. 44-Pin PLCC Z89223/273 Pin Description No Symbol Function 1 P2.0/INT0 Port 2.0/Interrupt 0 2 ED12/P0.12 External Data Bus/Port0 3 ED13/P0.13 External Data Bus/Port0 4 ED14/P0.14 External Data Bus/Port0 5 V Ground SS 6 ED15/P0.15 External Data Bus/Port0 7 ED3/P0.3 External Data Bus/Port0 8 ED4/P0.4 External Data Bus/Port0 9 V Ground SS 10 ED5/P0 ...
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... Digital Signal Processors with A/D Converter PIN CONFIGURATIONS (Continued) ED3/P0.3 ED4/P0.4 ED5/P0.5 ED6/P0.6 ED7/P0.7 ED8/P0.8 ED9/P0.9 ED10/P0.10 ED11/P0.11 Figure 4. 44-Pin PQFP Z89223/273 Pin Configuration 44-Pin PQFP RESET LPF 31 P2.2/TMO0/UO0 CLKO 29 CLKI P2.4/WAIT 27 DS P2.3/TMO1/UO1 25 EA2 EA1 23 EA0 DS000202-DSP0599 ZiLOG ...
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... ZiLOG Table 2. 44-Pin PQFP Z89223/273 Pin Description No Symbol Function 1 ED3/P0.3 External Data Bus/Port0 2 ED4/P0.4 External Data Bus/Port0 3 V Ground SS 4 ED5/P0.5 External Data Bus/Port0 5 ED6/P0.6 External Data Bus/Port0 6 ED7/P0.7 External Data Bus/Port0 7 ED8/P0.8 External Data Bus/Port0 8 ED9/P0.9 External Data Bus/Port0 9 V Ground ...
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... Digital Signal Processors with A/D Converter PIN CONFIGURATIONS (Continued ED0/P0.0 ED1/P0.1 ED2/P0.2 P1.0/INT2 V SS P1.1/CLKOUT P1.2/SDI P2.0/INT0 ED12/P0.12 ED13/P0. ED14/P0. ED15/P0.15 Figure 5. 64-Pin TQFP Z89323/373 Pin Configuration 64-Pin TQFP RD/ P2.1/INT1 V SS AN3 AN2 25 AN1 AN0 AGND P1.7/UI1 VALO P1.6/UI0 VAHI ED11/P0. DS000202-DSP0599 ZiLOG ...
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... ZiLOG Table 3. 64-Pin TQFP Z89223/273 Pin Description No Symbol Function 1 ED3/P0.3 External Data Bus/Port0 2 ED4/P0.4 External Data Bus/Port0 3 V Ground Power Supply DD 5 ED5/P0.5 External Data Bus/Port0 6 P1.3/SDO Port 1.3/Serial Output 7 ED6/P0.6 External Data Bus/Port0 8 P1.4/SS Port 1.4/Slave Select 9 ED7/P0.7 External Data Bus/Port0 10 P1 ...
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... Digital Signal Processors with A/D Converter PIN CONFIGURATIONS (Continued) NC ED3/P0.3 ED4/P0 ED5/P0.5 P1.3/SDO ED6/P0.6 P1.4/SS ED7/P0.7 P1.5/SCLK P2.7 ED8/P0.8 ED9/P0 ED10/P0. Figure 6. 68-Pin PLCC Z89323/373 Pin Configuration 68-Pin PLCC 26 27 ZiLOG RESET LPF P2.5/UI2 P2.2/TMO0/UO0 P2.6/TMO2 CLKO CLKI P2.4/WAIT DS P2.3/TMO1/UO1 EA2 EA1 EA0 44 HALT 43 DS000202-DSP0599 ...
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... ZiLOG Table 4. 68-Pin PLCC Z89323/373 Pin Description No Symbol Function 1 P1.2/SDI Port 1.2/Serial Input 2 P2.0/INT0 Port 2.0/Interrupt 0 3 ED12/P0.12 External Data Bus/Port0 4 ED13/P0.13 External Data Bus/Port0 Power Supply ED14/P0.14 External Data Bus/Port0 7 V Ground SS 8 ED15/P0.15 External Data Bus/Port0 Connection Connection 11 ED3/P0.3 External Data Bus/Port0 12 ED4/P0 ...
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... Digital Signal Processors with A/D Converter PIN CONFIGURATIONS (Continued P30 ED0/P0.0 ED1/P0.1 ED2/P0.2 P1.0/INT2 P1.1/CLKOUT P1.2/SDI P2.0/INT0 ED12/P0.12 75 ED13/P0. ED14/P0. P3 Figure 7. 80-Pin PQFP Z89323/373 Pin Configuration 80-Pin PQFP ZiLOG P2.1/INT1 V SS AN3 35 AN2 AN1 AN0 AGND P1.7/UI1 VALO 30 P1.6/UI0 V SS VAHI ED11/P0. DS000202-DSP0599 ...
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... ZiLOG Table 5. 80-Pin PQFP Z89323/373 Pin Description No Symbol Function Connection 2 ED15/P0.15 External Data Bus/Port0 Connection Connection 5 ED3/P0.3 External Data Bus/Port0 6 P3.2 Port 3.2 7 ED4/P0.4 External Data Bus/Port0 8 V Ground Power Supply DD 10 ED5/P0.5 External Data Bus/Port0 11 P1.3/SDO Port 1.3/Serial Output 12 ED6/P0.6 External Data Bus/Port0 13 P1 ...
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... Exposure to absolute maximum rating conditions for extended period may affect 0 70 °C device reliability. –40 85 °C I (+) I (–) From Output Under Test 30 pF 9.1 K Figure 8. Test Load Diagram DS000202-DSP0599 ZiLOG 2.1 K ...
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... ZiLOG DC ELECTRICAL CHARACTERISTICS Table 6. ROM Version –40°C to +85°C for “E” temperature range, unless otherwise noted; A Symbol Parameter I Supply Current using PLL DD–PLL I Supply Current using External Clock Direct DD–ECD I Supply Current using XTAL Oscillator Direct DD–XOD I Supply Current during Deep Sleep DD– ...
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... Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter DC ELECTRICAL CHARACTERISTICS (Continued Direct Clock with VCO Off PLL Clock from 32.8KHz Crystal Figure 9. Z89373 Typical OTP Current Consumption System Clock [MHz] ZiLOG 20 25 DS000202-DSP0599 ...
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... ZiLOG AC ELECTRICAL CHARACTERISTICS Table –40°C to +85°C for “E” temperature range, unless otherwise noted A Symbol Parameter Clock TCY CLKI Cycle Time for user-supplied clock CPWH CLKI Pulse Width High CPWL CLKI Pulse Width Low Tr CLKI Rise Time for 20-MHz user-supplied clock ...
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... Power Dissipation 20 Table 9. AV –AGND = 5V ±10% CC Min Typ 0.5 0 VALO 110 VALO + 2.5 AGND 2 Table 10. AV –AGND = 5V ±10% CC Min Typ 3 3 VALO 110 VALO + 2.5 AGND 2.5 5 ZiLOG Max Units 1 LSB 1 LSB 3 LSB 3 LSB VAHI µ Ð2 Max Units 1 LSB 1 LSB 4 LSB 4 ...
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... ZiLOG TIMING DIAGRAMS RD/WR DS EA(2:0) ED(15:0) RD/WR DS WLAT WAIT CLKOUT EA(2:0) ED(15:0) DS000202-DSP0599 16-Bit Digital Signal Processors with A/D Converter TCY CPWL Figure 10. Clock Timing RWSET EASET Valid Address Out RDSET Data Figure 11. Read Timing WDEA Valid Address Out RDSET Figure 12. Read Timing Using WAIT Pin ...
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... TIMING DIAGRAMS (Continued) RD/WR DS EA(2:0) ED(15:0) RD/WR RWSET DS WLAT WAIT CLKOUT EASET EA(2:0) WRVALID ED(15:0) 22 RWSET EASET Valid Address Out WRVALID Data Figure 13. Write Timing WDEA Valid Address Out Data Figure 14. Write Timing Using WAIT Pin ZiLOG RWHOLD EAHOLD WRHOLD RWHOLD WRHOLD DS000202-DSP0599 ...
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... ZiLOG SS* SS-SDO Valid SCLK* SCLK-SDO Valid SDO TRI-STATE SDI *Notes: The polarity of SCLK and SS are programmable by the user used in Slave Mode only. This figure illustrates data transmission on the falling edge of SCLK, data reception on the rising edge of SCLK, with SS active Low (default). ...
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... TMO1 on Port2. When the User Outputs are enabled, they are the complements of bits S5 and S6 of the Status Register. There is a switch that connects the DDATA 16 Multiplier Unit Output 24 MUX 24 24 ALU 24 Accumulator (24) 16 MSB Figure 17. ALU Block Diagram A six-level hardware stack is connected The Z893x3 features three DS000202-DSP0599 ZiLOG ...
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... ZiLOG The Z893x3 features three user interrupt inputs Interrupts. which can be programmed to be positive or negative edge- triggered. There are five interrupts generated by internal pe- ripherals: the A/D converter, the Serial Peripheral Interface, and the three Counter/Timers. Internally there are three pri- ority levels. The internal signals for Interrupt service Re- quests are denoted ISR0, ISR1, and ISR2, with ISR0 having the highest priority, and ISR2 the lowest ...
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... The first 16 locations of each n = pointer number = bank = thus, D0:0, D1:0, D2:0, D3:0 for RAM0 D0:1, D1:1, D2:1, D3:1 for RAM1 If S3/ the status register, then D0:0/D1:0/D2:0/D3:0 refer to register locations 4/5/6/7 in data RAM Bank 0. FFFF FFFC Not Used 1FFF-D 1FFC 1FFB 0000 DS000202-DSP0599 ZiLOG ...
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... ZiLOG REGISTERS Both external and internal registers are accessed in one ma- chine cycle. The external registers are used to access the on- chip peripherals when they are enabled. The internal registers of the Z893X3 are defined below: Register Register Definition X Multiplier X Input, 16-bits Y Multiplier Y Input, 16-bits ...
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... EXT0–EXT6, and is not available for accessing an external peripheral UI1 UI0 SH3 OP IE UO1 UO0 S12 S11 S10 Figure 19. Status Register RPL Ram Pointer "Short Form Direct" bits User Output UO1, UO0 (Complemented) Global Interrupt Enable DS000202-DSP0599 ZiLOG Loop Size 256 128 ...
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... ZiLOG BANK/EXT REGISTER ASSIGNMENTS There are 16 different Banks of EXT registers. Control of the bank switching is done via the EXT7 register. The same EXT7 register exists in all Banks. Banks 0–5 support different combinations of external reg- isters for external peripherals, and external registers for in- ternal (on-chip) peripherals ...
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... Performing these steps clear all of the interrupts that were pending, but leave the Register Bank Select unchanged Figure 20. EXT7 Register ZiLOG Bank Select 0000 : Bank0 0001 : Bank1 : : 1111 : Bank15 Interrupt Status Bits Bit 4 = A/D Finish Interrupt Bit 5 = SPI Interrupt Bit 6 = Timer0 Interrupt ...
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... ZiLOG Interrupt Allocation Register Bits 3–0 of the Interrupt Allocation Register define which unique interrupt source the highest priority, and is allocated to ISR0 (Interrupt Service Request 0). Bits 7–4 of the Interrupt Allocation Register define which unique interrupt source has the second highest priority, and is allocated to ISR1 (Interrupt Service Request 1) ...
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... Wait-State EXT2 10 = read (ws), write (ws) Wait-State EXT3 11 = read (ws), write (ws) Wait-State EXT4 nws = no wait state ws = one wait state Wait-State EXT5 Wait-State EXT6 Bit14 Disabled WAIT Input Pin (default Enabled P2.4 as WAIT Input Pin Bit 15 Disabled UO0, UO1 (default Enable UO0, UO1 DS000202-DSP0599 ZiLOG ...
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... ZiLOG I/O PORTS I/O pin allocation of ports for the different package types is designed to provide configuration flexibility. Each port line of Ports 0, 1, and 2 can be independently selected as 44-Pin PLCC, Device Pins 44-Pin PQFP P0 MSB ED15–ED8, or P0.15–P0.8, or P1.7–P1.0 P0 LSB ED7–ED0, or P0.7– ...
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... P1.7–P1.0 Pins 7–0 P0.7–P0.0 110 = Reserved 111 = Reserved INT2 0 = Disabled (default Enabled INT1 0 = Disabled (default Enabled CLKOUT 0 = Disabled (default Enabled Port1 Outputs 0 = Push-Pull (default Open-Drain Port0 Outputs 0 = Push-Pull (default Open-Drain Port I/O Output Bit Directions 0 = Input (default Output DS000202-DSP0599 ZiLOG ...
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... ZiLOG Port1Ñ8-Bit Programmable I/O Bank15/EXT1 is the Port1 control register. The MSB is the Port1 direction control. Port1 data is accessed as the LSB of EXT5 in Banks The Port1 pins can also be mapped to internal functions. When INT2, CLKOUT, UI0 Port Pin IF P1.0/INT2 Bank15/EXT1 Bit P1.1/CLKOUT Bank15/EXT1 Bit ...
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... Counter/Timer2 Operation 0 = Stopped (default Counting If D15 = 0, Counter/Timer2 Clock defined System Clock/2 (default UI2 If D15 = 1, Counter/Timer2 Sleep Mode Wake- Disabled (default Enabled TMO2 0 = Disabled (default Enabled Counter/Timer2 Clock 0 = Defined by D13 (default CLKI DS000202-DSP0599 ZiLOG Else P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 ...
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... ZiLOG Port3Ñ8-BIt Programmable I/O Port3 is an additional I/O port available only in the 80-pin package. P3.3–P3.0 are inputs and P3.7–P3.4 are outputs. Bit 8 of Bank15/EXT2 enables and disables Port3. The LSB of Bank2/EXT5 is the Port3 Data Register. DS000202-DSP0599 Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter ...
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... The relative error of the converter will increase and the con- version time will also take longer. ISR1 C/T0 C/T2 ADCTL Reg. Start Converter A/D Prescaler Channel Select Sample Half-Flash and A/D Hold Converter Figure 28. ADC Architecture ZiLOG A/D Control Register Internal Bus Quad Scan 4x8 Result Register DS000202-DSP0599 ...
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... ZiLOG Bank13/EXT0 (LSB CSEL0 CSEL1 (Reserved) SCAN QUAD DIV0 DIV1 DIV2 Figure 29. ADCTL Register (LSB) Table 18. A/D Prescaler Values (Bits DIV2 DIV1 DIV0 Table 19. Operating Modes (Bits 4, 3) QUAD SCAN Option 0 0 Convert selected channel 4 times, then stop 0 1 Convert selected channel, then stop ...
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... Input edges may be selected as rising, falling, or both. UI1 UI0 0 15 Timer Load Register MUX 15 16-Bit Down Counter 2 TMCLKIN = System Clock 2 x (TPR + 1) ZiLOG The C/T is con- The C/T is con- The C/T is configured to The C/T is config- The C/T is configured to count The C/T is configured TMLR 0 TMR ...
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... ZiLOG Bank 13/EXT1 (C/T0) and Bank14/EXT1 (C/T1) D15 D14 D13 D12 D11 D10 D9 D8 *Note: The user should always program this bit to "0". C/T Registers Each C/T contains a set of five 16-bit Registers. Bank13 is used to access the registers for C/T0 and Bank14 is for the C/T1 registers ...
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... Note: For C/T Modes 8–11, the external input signal on UI0 or Prescaler UI1 is synchronized with TMCLKIN before being ap- plied to TMR. The external input signal frequency must be no higher than 1/2 of the TMCLKIN frequency Bank 13,14/EXT5 TPR 8-Bit Counter Figure 36. TPR—Prescaler Register DS000202-DSP0599 ZiLOG ...
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... ZiLOG GENERAL-PURPOSE COUNTER/TIMER (C/T2) This versatile16-bit C/T offers multiple uses, including Sleep Mode Wake-up. It can be clocked with the slow 32 kHz crystal clock (CLKI), while the DSP and other pe- ripheral functions operate at a higher frequency generated by the PLL. Also included is an independent long duration timer ...
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... Port2 Outputs 0 = Push-Pull (default Open-Drain Counter/Timer2 0 = Disabled (default Enabled Counter/Timer2 Operation 0 = Stopped (default Counting If D15 = 0, Counter/Timer2 Clock defined System Clock/2 (default UI2 If D15 = 1, Counter/Timer2 Sleep Mode Wake- Disabled (default Enabled TMO2 0 = Disabled (default Enabled Counter/Timer2 Clock 0 = Defined by D13 (default CLKI DS000202-DSP0599 ZiLOG ...
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... ZiLOG SERIAL PERIPHERAL INTERFACE The Z893x3 incorporates a Serial Peripheral Interface (SPI) for communication with other microcontrollers and periph- erals. The SPI can be operated either as the system Master system Slave. The SPI consists of three registers: the SPI Control Register (Bank15/EXT4), the SPI Re- ceive/Buffer Register (RxBUF), and the SPI Shift Register ...
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... During slave operation, SCLK is an input. Note: Slave Mode is not available on the 44-pin package. System Clock (from PLL Block) SPI Shift Register SPI Receive Buffer (RxBuf) SPI Control (SCON) Figure 41. SPI Block Diagram ZiLOG SCLK/P1.5 SPI• I/O SDO/P1.3 SDI/P1.2 SS/P1.4 DS000202-DSP0599 ...
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... ZiLOG SYSTEM CLOCK GENERATOR The System Clock can be generated from an external clock signal, or from the internal crystal oscillator. For the latter case, a 32-kHz crystal is used in conjunction with the in- ternal crystal oscillator. The system clock generator in- cludes a Phase-Locked Loop (PLL) circuit to derive a high- frequency System Clock from the low-frequency crystal os- cillator ...
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... Twice the Crystal Frequency Recovery Source 00 : POR (Power-On Reset) or Port 2, Bit 0 (INT0 POR or Port 1, Bit 4 (SS POR or Port 1, Bit 6 (UI0 POR or Port 2, Bit 0 or Port 1, Bit 4 or Port 1, Bit 6 STOP Recovery Level 0 : Low (Default setting after reset High DS000202-DSP0599 ZiLOG Sys Clk Sel ...
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... ZiLOG INSTRUCTION SET The addressing modes are: <pregs>, <hwregs>. These modes are used for loads to and from registers within the chip, such as loading to the accumulator, or loading from a pointer register. The names of the registers are specified in the operand field (destination first, then source). ...
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... NIE Not Interrupts Enabled NOV Not Overflow NU0 Not User Zero NU1 Not User One NZ Not zero OV Overflow PL Plus (Positive) U0 User Zero U1 User One UGE Unsigned Greater Than or Equal (Same as NC) ULT Unsigned Less Than (Same Zero 50 ZiLOG DS000202-DSP0599 ...
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... ZiLOG INSTRUCTION DESCRIPTIONS Inst. Description Synopsis ABS Absolute ABS[<cc>,]<src> Value ADD Addition ADD<dest>,<src> AND Bitwise AND AND<dest>,<src> CALL Subroutine CALL call [<cc>,]<address> CCF Clear C flag CCF CIEF Clear IE Flag CIEF COPF Clear OP flag COPF CP Comparison CP<src1>,<src2> ...
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... ZiLOG A,D0 A,P0 A,@P1 A,@D0 A,124 1 LD 124 D0:0,EXT7 1 LD P1:1,#% P1:1,EXT1 1 ...
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... ZiLOG Inst. Description Synopsis Notes: If src1 is <regind> it must be a bank 1 register. Src2’s <regind> must be a bank 0 register. <hwregs> for src1 cannot be X. For the operands <hwregs>, <regind> the <bank switch> defaults to OFF. For the operands <regind>, <regind> the <bank switch> defaults to ON. ...
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... A,<regind> 1 A,<hwregs> 1 A,<simm> 1 switch. These keywords are referenced in the instruction de- scriptions through the <bank switch> symbol. The most no- table capability is that a source operand can be multiplied by itself (squared). ZiLOG 1 XOR A,P2:0 1 XOR A,D0:1 2 XOR A,#13933 3 XOR A,@@P2:1+ 1 XOR A,%2F ...
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... ZiLOG PACKAGE INFORMATION DS000202-DSP0599 16-Bit Digital Signal Processors with A/D Converter Figure 44. 44-Pin PLCC Package Diagram Figure 45. 44-Pin PQFP Package Diagram Z89223/273/323/373 55 ...
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... Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter PACKAGE INFORMATION (Continued) 56 Figure 46. 64-Pin TQFP Package Diagram ZiLOG DS000202-DSP0599 ...
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... ZiLOG DS000202-DSP0599 16-Bit Digital Signal Processors with A/D Converter Figure 47. 68-Pin PLCC Package Diagram Z89223/273/323/373 57 ...
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... Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter PACKAGE INFORMATION (Continued) 58 Figure 48. 80-Pin PQFP Package Diagram ZiLOG DS000202-DSP0599 ...
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... TQFP Z8932320ASC Z8932320AEC 68-Pin PLCC Z8932320VSC Z8932320VEC 80-Pin PQFP Z8932320FSC Z8932320FEC For fast results, contact your local ZiLOG sales office for assistance in ordering the part required. CODES Package V = PLCC A = TQFP F = PQFP Temperature S = 0°C to +70° –40°C to 85°C ...
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... Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter ©1999 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT ...