XCR3256XL-7PQ208C Xilinx Inc, XCR3256XL-7PQ208C Datasheet - Page 13

• Manufacturer Part Number: XCR3256XL-7PQ208C
• Description: IC CPLD 256MCELL 3.3V HP 208PQFP
• Manufacturer: Xilinx Inc
• Series: CoolRunner XPLA3r

Specifications of XCR3256XL-7PQ208C

• Programmable Type: In System Programmable (min 1K program/erase cycles)
• Delay Time Tpd(1) Max: 7.0ns
• Voltage Supply - Internal: 3 V ~ 3.6 V
• Number Of Logic Elements/blocks: 16
• Number Of Macrocells: 256
• Number Of Gates: 6000
• Number Of I /o: 164
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Voltage: 3.3V
• Memory Type: EEPROM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -

DS013 (v2.7) March 31, 2006
Product Specification
01/08/02
11/20/02
01/27/03
07/15/03
08/21/03
02/13/04
04/08/05
03/31/06
11/5/03
Date
R
Version
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Moved ICC vs Freq.
to AC Table, renamed T
to match software timing. Added T
correct a typo. Updated AC Load Circuit diagram to more closely resemble true test
conditions, added note for T
Updated T
Updated the following specs based on characterization of product after move to UMC
fabrication: f
Derating Curve for T
characterization data. Updated ordering information to new format.
Moved incorrect note for V
Updated test conditions for I
Updated Package Device Marking Pin 1 orientation.
Updated from Preliminary Product Specification to Product Specification.
Add Tsol specification. Add links to application notes and data sheets.
Added I
Added Warranty Disclaimer. Added Pb-Free ordering information.
CCSB
PCO
SYSTEM
Typical and T
(added T
, V
Figure 1
PD2
OH
www.xilinx.com
SU
PTCK
(improved to 6.5 ns for 16 outputs switching) per new
,T
to T
OH
APRPW
CONFIG
POD
IL
), T
and
to line 2 from line 3 in DC table.
SU2
and I
FIN
delay measurement.
Table 1
, T
specifications. Removed T
for setup time through the OR array. Updated T
INIT
, and T
IH
INIT
.
spec. Updated T
, T
Revision
to page 1. Added single p-term setup time (T
OUT
LOGI3,
to match timing model and software.
T
F
. Updated Typical I
CONFIG
XCR3256XL 256 Macrocell CPLD
SOL
spec. Updated T
specification.
CC
vs. Freq. and
HI
SUF
spec to
spec
SU1
)
13