EPM7256AETI144-7N Altera, EPM7256AETI144-7N Datasheet - Page 53
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EPM7256AETI144-7N
Manufacturer Part Number
EPM7256AETI144-7N
Description
IC MAX 7000 CPLD 256 144-TQFP
Manufacturer
Altera
Series
MAX® 7000Ar
Datasheet
1.EPM7032AELC44-10N.pdf
(64 pages)
Specifications of EPM7256AETI144-7N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
16
Number Of Macrocells
256
Number Of Gates
5000
Number Of I /o
120
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
144-TQFP, 144-VQFP
Voltage
3.3V
Memory Type
EEPROM
Number Of Logic Elements/cells
16
Family Name
MAX 7000A
# Macrocells
256
Number Of Usable Gates
5000
Frequency (max)
166.67MHz
Propagation Delay Time
7.5ns
Number Of Logic Blocks/elements
16
# I/os (max)
120
Operating Supply Voltage (typ)
3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2063
EPM7256AETI144-7N
EPM7256AETI144-7N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM7256AETI144-7N
Manufacturer:
SPANSION
Quantity:
1 001
Company:
Part Number:
EPM7256AETI144-7N
Manufacturer:
ALTERA
Quantity:
40
Company:
Part Number:
EPM7256AETI144-7N
Manufacturer:
ALTERA
Quantity:
3 530
Altera Corporation
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t
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Symbol
IN
IO
FIN
SEXP
PEXP
LAD
LAC
IOE
OD1
OD2
OD3
ZX1
ZX2
ZX3
XZ
SU
H
FSU
FH
RD
Table 30. EPM7256A Internal Timing Parameters (Part 1 of 2)
Input pad and buffer delay
I/O input pad and buffer
delay
Fast input delay
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable
delay
Output buffer and pad
delay, slow slew rate = off
V
Output buffer and pad
delay, slow slew rate = off
V
Output buffer and pad
delay slow slew rate = on
V
Output buffer enable
delay slow slew rate = off
V
Output buffer enable
delay slow slew rate = off
V
Output buffer enable
delay slow slew rate = on
V
Output buffer disable
delay
Register setup time
Register hold time
Register setup time of fast
input
Register hold time of fast
input
Register delay
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
= 3.3 V
= 2.5 V
= 2.5 V or 3.3 V
= 3.3 V
= 2.5 V
= 2.5 V or 3.3 V
Parameter
C1 = 35 pF
C1 = 35 pF
(5)
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
(5)
C1 = 35 pF
C1 = 5 pF
Conditions
Min
1.0
1.7
1.2
1.3
-6
MAX 7000A Programmable Logic Device Data Sheet
Max
2.5
0.3
0.3
2.4
2.8
0.5
2.5
0.2
0.3
0.8
5.3
4.0
4.5
9.0
4.0
1.6
Min
1.3
2.4
1.4
1.6
-7
Note (1)
Speed Grade
Max
0.4
0.4
3.0
3.5
0.6
3.1
3.1
0.3
0.4
0.9
5.4
4.0
4.5
9.0
4.0
2.0
Min
1.7
3.7
1.4
1.6
-10
Max
10.0
0.5
0.5
3.4
4.7
0.8
4.2
4.2
0.4
0.5
1.0
5.5
5.0
5.5
5.0
2.7
Min
2.0
4.7
1.4
1.6
-12
Max
10.0
0.6
0.6
3.8
5.6
1.0
5.0
5.0
0.5
0.6
1.1
5.6
5.0
5.5
5.0
3.2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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