EPM570F256I5N Altera, EPM570F256I5N Datasheet - Page 69

• Manufacturer Part Number: EPM570F256I5N
• Description: IC MAX II CPLD 570 LE 256-FBGA
• Manufacturer: Altera
• Series: MAX® IIr

Specifications of EPM570F256I5N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 5.4ns
• Voltage Supply - Internal: 2.5V, 3.3V
• Number Of Logic Elements/blocks: 570
• Number Of Macrocells: 440
• Number Of I /o: 160
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 256-FBGA
• Voltage: 2.5V, 3.3V
• Memory Type: FLASH
• Number Of Logic Elements/cells: 570
• Family Name: MAX II
• # Macrocells: 440
• Frequency (max): 1.8797GHz
• Propagation Delay Time: 8.7ns
• Number Of Logic Blocks/elements: 57
• # I/os (max): 160
• Operating Supply Voltage (typ): 2.5/3.3V
• In System Programmable: Yes
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: FBGA
• No. Of I/o's: 160
• Propagation Delay: 8.7ns
• Global Clock Setup Time: 1.9ns
• Frequency: 201.1MHz
• Supply Voltage Range: 2.375V To 2.625V, 3V To 3.6V
• Operating Temperature Range: -40°C To +100°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1399; EPM570F256I5N

Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
Internal Timing Parameters
Table 5–15. LE Internal Timing Microparameters
© August 2009 Altera Corporation
Symbol
t
t
t
t
t
t
t
t
t
LUT
COM B
CLR
PRE
SU
H
CO
CLK HL
C
LE combinational
LUT delay
Combinational
path delay
LE register clear
delay
LE register preset
delay
LE register setup
time before clock
LE register hold
time after clock
LE register clock-
to-output delay
Minimum clock
high or low time
Register control
delay
f
Parameter
Internal timing parameters are specified on a speed grade basis independent of device
density.
microparameters for logic elements (LEs), input/output elements (IOEs), UFM
blocks, and MultiTrack interconnects. The timing values for –3, –4, and –5 speed
grades shown in
target, while –6, –7, and –8 speed grade values are based on an EPM570Z device
target.
For more explanations and descriptions about each internal timing microparameters
symbol, refer to the
Device Handbook.
Min
238
238
208
166
–3 Speed
—
—
—
—
0
Table 5–15
Grade
Max Min
571
147
235
857
—
—
—
—
—
MAX II / MAX IIG
Table 5–15
309
309
271
216
—
—
—
—
through
–4 Speed
0
Understanding Timing in MAX II Devices
Grade
1,114
Max
742
192
305
—
—
—
—
—
Table 5–22
through
Min
381
381
333
266
—
—
—
—
–5 Speed
0
Grade
1,372
Table 5–22
Max
914
236
376
—
—
—
—
—
describe the MAX II device internal timing
Min
401
401
260
253
—
—
—
—
–6 Speed
0
Grade
are based on an EPM1270 device
1,215
1,356
Max
243
380
—
—
—
—
—
Min
541
541
319
335
—
—
—
—
–7 Speed
0
MAX IIZ
Grade
chapter in the MAX II
2,247
1,722
Max
305
489
—
—
—
—
—
MAX II Device Handbook
Min
545
545
321
339
—
—
—
—
0
–8 Speed
Grade
2,247
1,741
Max
309
494
—
—
—
—
—
Unit
5–11
ps
ps
ps
ps
ps
ps
ps
ps
ps