EPM570F256I5N Altera, EPM570F256I5N Datasheet - Page 57
![IC MAX II CPLD 570 LE 256-FBGA](/photos/6/70/67063/544-256-fbga_sml.jpg)
EPM570F256I5N
Manufacturer Part Number
EPM570F256I5N
Description
IC MAX II CPLD 570 LE 256-FBGA
Manufacturer
Altera
Series
MAX® IIr
Specifications of EPM570F256I5N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
5.4ns
Voltage Supply - Internal
2.5V, 3.3V
Number Of Logic Elements/blocks
570
Number Of Macrocells
440
Number Of I /o
160
Operating Temperature
-40°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
256-FBGA
Voltage
2.5V, 3.3V
Memory Type
FLASH
Number Of Logic Elements/cells
570
Family Name
MAX II
# Macrocells
440
Frequency (max)
1.8797GHz
Propagation Delay Time
8.7ns
Number Of Logic Blocks/elements
57
# I/os (max)
160
Operating Supply Voltage (typ)
2.5/3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
256
Package Type
FBGA
No. Of I/o's
160
Propagation Delay
8.7ns
Global Clock Setup Time
1.9ns
Frequency
201.1MHz
Supply Voltage Range
2.375V To 2.625V, 3V To 3.6V
Operating Temperature Range
-40°C To +100°C
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1399
EPM570F256I5N
EPM570F256I5N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM570F256I5N
Manufacturer:
ALTERA
Quantity:
26
Part Number:
EPM570F256I5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Chapter 4: Hot Socketing and Power-On Reset in MAX II Devices
Power-On Reset Circuitry
Figure 4–5. Power-Up Characteristics for MAX II, MAX IIG, and MAX IIZ Devices
Notes to
(1) Time scale is relative.
(2)
© October 2008 Altera Corporation
Figure 4–5
Figure
1.55 V
1.55 V
3.3 V
1.8 V
1.4 V
3.3 V
2.5 V
1.7 V
1.4 V
3.3 V
1.8 V
1.4 V
0 V
0 V
0 V
V
V
V
assumes all V
4–5:
CCINT
CCINT
CCINT
1
After SRAM configuration, all registers in the device are cleared and released into
user function before I/O tri-states are released. To release clears after tri-states are
released, use the DEV_CLRn pin option. To hold the tri-states beyond the power-up
configuration time, use the DEV_OE pin option.
CCIO
Tri-State
Tri-State
Tri-State
banks power up simultaneously with the V
t
t
t
CONFIG
CONFIG
CONFIG
MAX II Device
MAX IIG Device
MAX IIZ Device
Approximate Voltage
for SRAM Download Start
User Mode
User Mode
Operation
Operation
User Mode
Operation
minimum 10 µs
CCINT
profile shown. If not, t
V
Approximate Voltage
for SRAM Download Start
CCINT
Approximate Voltage
for SRAM Download Start
dips below this level
Tri-State
to 0 V if the V
must be powered down
Tri-State
Tri-State
CONFIG
(Note
CCINT
Device Resets
the SRAM and
Tri-States I/O Pins
stretches out until all V
Device Resets
the SRAM and
Tri-States I/O Pins
1),
(2)
t
User Mode
CONFIG
Operation
MAX II Device Handbook
CCIO
banks are powered.
4–7