EPM570F256I5N Altera, EPM570F256I5N Datasheet - Page 22
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EPM570F256I5N
Manufacturer Part Number
EPM570F256I5N
Description
IC MAX II CPLD 570 LE 256-FBGA
Manufacturer
Altera
Series
MAX® IIr
Specifications of EPM570F256I5N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
5.4ns
Voltage Supply - Internal
2.5V, 3.3V
Number Of Logic Elements/blocks
570
Number Of Macrocells
440
Number Of I /o
160
Operating Temperature
-40°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
256-FBGA
Voltage
2.5V, 3.3V
Memory Type
FLASH
Number Of Logic Elements/cells
570
Family Name
MAX II
# Macrocells
440
Frequency (max)
1.8797GHz
Propagation Delay Time
8.7ns
Number Of Logic Blocks/elements
57
# I/os (max)
160
Operating Supply Voltage (typ)
2.5/3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
256
Package Type
FBGA
No. Of I/o's
160
Propagation Delay
8.7ns
Global Clock Setup Time
1.9ns
Frequency
201.1MHz
Supply Voltage Range
2.375V To 2.625V, 3V To 3.6V
Operating Temperature Range
-40°C To +100°C
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1399
EPM570F256I5N
EPM570F256I5N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM570F256I5N
Manufacturer:
ALTERA
Quantity:
26
Part Number:
EPM570F256I5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
2–14
MAX II Device Handbook
functions from LE 1 to LE 10 in the same LAB. The register chain connection allows
the register output of one LE to connect directly to the register input of the next LE in
the LAB for fast shift registers. The Quartus II Compiler automatically takes
advantage of these resources to improve utilization and performance.
shows the LUT chain and register chain interconnects.
Figure 2–11. LUT Chain and Register Chain Interconnects
The C4 interconnects span four LABs up or down from a source LAB. Every LAB has
its own set of C4 interconnects to drive either up or down.
interconnect connections from an LAB in a column. The C4 interconnects can drive
and be driven by column and row IOEs. For LAB interconnection, a primary LAB or
its vertical LAB neighbor can drive a given C4 interconnect. C4 interconnects can
drive each other to extend their range as well as drive row interconnects for column-
to-column connections.
Interconnect
Adjacent LE
Routing to
LUT Chain
Local
Local Interconnect
Routing Among LEs
in the LAB
LE6
LE0
LE1
LE2
LE3
LE4
LE5
LE7
LE8
LE9
Register Chain
Routing to Adjacent
LE's Register Input
Figure 2–12
© October 2008 Altera Corporation
Chapter 2: MAX II Architecture
MultiTrack Interconnect
Figure 2–11
shows the C4