EPM3032ATC44-7 Altera, EPM3032ATC44-7 Datasheet - Page 11
![IC MAX 3000A CPLD 32 44-TQFP](/photos/6/70/67053/544-44-tqfp_sml.jpg)
EPM3032ATC44-7
Manufacturer Part Number
EPM3032ATC44-7
Description
IC MAX 3000A CPLD 32 44-TQFP
Manufacturer
Altera
Series
MAX® 3000Ar
Datasheet
1.EPM3032ATC44-10N.pdf
(46 pages)
Specifications of EPM3032ATC44-7
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
2
Number Of Macrocells
32
Number Of Gates
600
Number Of I /o
34
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
44-TQFP, 44-VQFP
Voltage
3.0 V ~ 3.6 V
Memory Type
EEPROM
Number Of Logic Elements/cells
2
Family Name
MAX 3000A
# Macrocells
32
Number Of Usable Gates
600
Frequency (max)
166.67MHz
Propagation Delay Time
7.5ns
Number Of Logic Blocks/elements
2
# I/os (max)
34
Operating Supply Voltage (typ)
3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
44
Package Type
TQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1153
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM3032ATC44-7
Manufacturer:
ALTERA
Quantity:
30
Part Number:
EPM3032ATC44-7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EPM3032ATC44-7N/I44-10N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
MAX 3000A Programmable Logic Device Family Data Sheet
Figure 5. MAX 3000A PIA Routing
To LAB
PIA Signals
While the routing delays of channel–based routing schemes in masked or
FPGAs are cumulative, variable, and path–dependent, the MAX 3000A
PIA has a predictable delay. The PIA makes a design’s timing
performance easy to predict.
I/O Control Blocks
The I/O control block allows each I/O pin to be individually configured
for input, output, or bidirectional operation. All I/O pins have a tri–state
buffer that is individually controlled by one of the global output enable
signals or directly connected to ground or V
.
Figure 6
shows the I/O
CC
control block for MAX 3000A devices. The I/O control block has 6 or
10 global output enable signals that are driven by the true or complement
of two output enable signals, a subset of the I/O pins, or a subset of the
I/O macrocells.
Altera Corporation
11