EPM3032A Altera Corporation, EPM3032A Datasheet
EPM3032A
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EPM3032A Summary of contents
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... December 2002, ver. 3.2 Features... Table 1. MAX 3000A Device Features Feature EPM3032A Usable gates 600 Macrocells 32 Logic array blocks 2 Maximum user I/O 34 pins t (ns) 4 (ns) 2 (ns) 3.0 CO1 f (MHz) 227.3 CNT Altera Corporation DS-MAX3000A-3.2 ® High–performance, low–cost CMOS EEPROM–based programmable logic devices (PLDs) built on a MAX 3.3-V in-system programmability (ISP) through the built– ...
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... BitBlaster well as programming hardware from third–party manufacturers and any in–circuit tester that supports Jam Programming Language (STAPL) Files (.jam), Jam STAPL Byte-Code Files (.jbc), or Serial Vector Format Files (.svf) TM serial download cable as TM Standard Test and Table 2. Altera Corporation TM ...
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... PALs, GALs, and 22V10s to MACH and pLSI devices. MAX 3000A devices are available in a wide range of packages, including PLCC, PQFP, and TQFP packages. See Table 3. MAX 3000A Maximum User I/O Pins Device 44–Pin 44–Pin PLCC EPM3032A 34 EPM3064A 34 EPM3128A EPM3256A EPM3512A Note: (1) When the IEEE Std. 1149.1 (JTAG) interface is used for in– ...
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... I/O pin. 4 Logic array blocks (LABs) Macrocells Expander product terms (shareable and parallel) Programmable interconnect array (PIA) I/O control blocks Figure 1 shows the architecture of MAX 3000A devices. MAX+PLUS II and the Sheet. Altera Corporation ...
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... Output Enables (1) I/O Control I/O Block I/O Control I/O Block Note: (1) EPM3032A, EPM3064A, EPM3128A, and EPM3256A devices have six output enables. EPM3512A devices have 10 output enables. Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet LAB Macrocells ...
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... Shareable expanders, which are inverted product terms that are fed back into the logic array Parallel expanders, which are product terms borrowed from adjacent macrocells shows a MAX 3000A macrocell. Global Clocks 2 Programmable Register Register Bypass PRN D/T Q Clock/ Enable ENA CLRN Select VCC To PIA Altera Corporation To I/O Control Block ...
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... Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet For registered functions, each macrocell flipflop can be individually programmed to implement operation with programmable clock control. The flipflop can be bypassed for combinatorial operation. During design entry, the designer specifies the desired flipflop type; the ...
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... LAB Figure 3 shows how shareable expanders can feed multiple SEXP Shareable expanders can be shared by any or all macrocells in an LAB. 36 Signals 16 Shared from PIA Expanders Macrocell Product-Term Logic Product-Term Select Matrix Macrocell Product-Term Logic Altera Corporation ...
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... Signals 16 Shared from PIA Expanders Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet The Altera development system compiler can automatically allocate up to three sets five parallel expanders to the macrocells that require additional product terms. Each set of five parallel expanders incurs a ...
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... MAX 3000A devices. The I/O control block has global output enable signals that are driven by the true or complement of two output enable signals, a subset of the I/O pins subset of the I/O macrocells. 10 Figure 5 PIA Signals shows how the PIA signals are routed . Figure 6 shows the I/O CC Altera Corporation To LAB ...
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... Figure 6. I/O Control Block of MAX 3000A Devices PIA Note: (1) EPM3032A, EPM3064A, EPM3128A, and EPM3256A devices have six output enables. EPM3512A devices have 10 output enables. Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet to Other I/O Pins from Macrocell to PIA When the tri–state buffer control is connected to ground, the output is tri-stated (high impedance), and the I/O pin can be used as a dedicated input. When the tri– ...
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... Hardware f For more information, see the 12 Application Note 88 (Using the Jam Language for ISP & ICR via Processor), Application Note 122 (Using Jam STAPL for ISP & and AN 111 (Embedded Programming Using Byte-Code). Altera Programming Hardware Data Sheet. Altera Corporation ...
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... MasterBlaster, ByteBlasterMV, or BitBlaster cable, or when using a Jam STAPL file, JBC file, or SVF file via an embedded processor or test equipment Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet The Altera software can use text– or waveform–format test vectors created with the Altera Text Editor or Waveform Editor to test the programmed device ...
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... Device EPM3032A EPM3064A EPM3128A EPM3256A EPM3512A Table 6. 32–Bit MAX 3000A Device IDCODE Value Device Version Part Number (16 Bits) (4 Bits) EPM3032A 0001 0111 0000 0011 0010 EPM3064A 0001 0111 0000 0110 0100 EPM3128A 0001 0111 0001 0010 1000 EPM3256A 0001 0111 0010 0101 0110 ...
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... Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Figure 7 shows the timing information for the JTAG signals. Figure 7. MAX 3000A JTAG Waveforms TMS TDI t JCP t t JCH JCL TCK t JPZX TDO t JSSU Signal to Be Captured t JSZX Signal to Be Driven ...
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... CCIO 2.5 v 2.5 v 3.3 When MAX 3000A device can drive a 2.5–V device that has 3.3–V CCIO tolerant inputs. ) for the t LPA LAD levels lower than 3.0 V CCIO instead of t OD2 OD1 Output Signal (V) 3.3 5.0 2 Altera Corporation , LAC IC . Inputs can 3.3 5 ...
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... Design Security Generic Testing Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Open–Drain Output Option MAX 3000A devices provide an optional open–drain (equivalent to open-collector) output for each I/O pin. This open–drain output enables the device to provide system–level control signals (e.g., interrupt and write enable signals) that can be asserted by any of several devices. It can also provide an additional wired– ...
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... PQFP and TQFP packages, under bias 703 [521 ] Device Output 620 [481 ] Device input rise and fall times < Note (1) Min (2) –0.5 –2.0 –25 –65 –65 Altera Corporation VCC To Test System C1 (includes jig capacitance) Max Unit 4 150 ° C 135 ° C 135 ° C ...
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... Input leakage current I I Tri–state output off–state current OZ R Value of I/O pin pull–up resistor when programming in–system or during power–up Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Conditions (10) (3) For commercial use For commercial use Note (4) Conditions I = – ...
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... MAX 3000A Min Max 8 8 and V CCINT CCIO Table 10 on page parameter refers OH parameter refers to OL pin (high–voltage pin during programming) voltage level for POR is CCINT reaches the sufficient POR voltage level. Altera Corporation Unit pF pF are 19. ...
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... Power Sequencing & Hot–Socketing Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Figure 9. Output Drive Characteristics of MAX 3000A Devices 3.3 V 150 100 Typical I O Output Current (mA 2.5 V 150 100 Typical I O Output Current (mA Because MAX 3000A devices can be used in a mixed–voltage environment, they have been designed specifically to tolerate any possible power– ...
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... Control Delay t LAC Shared Expander Delay t SEXP Figure 10. MAX 3000A Output Register Delay Delay OD1 OD2 t t PRE OD3 t t CLR COMB Figure 11 shows the timing relationship Altera Corporation I/O Delay ...
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... F driven for a logic high and 0 V for a logic low. All timing characteristics are measured at 1.5 V. Shared Expander Parallel Expander (Logic Array Output) Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Combinatorial Mode t IN Input Pin t IO I/O Pin PIA Delay ...
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... MAX 3000A Programmable Logic Device Family Data Sheet Tables 13 EPM3256A, and EPM3512A timing information. Table 13. EPM3032A External Timing Parameters Symbol Parameter t Input to non– PD1 registered output t I/O input to non– PD2 registered output t Global clock setup SU time t Global clock hold time ...
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... Table 14. EPM3032A Internal Timing Parameters (Part Symbol Parameter t Input pad and buffer delay IN t I/O input pad and buffer IO delay t Shared expander delay SEXP t Parallel expander delay PEXP t Logic array delay LAD t Logic control array delay LAC t Internal output enable delay ...
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... MAX 3000A Programmable Logic Device Family Data Sheet Table 14. EPM3032A Internal Timing Parameters (Part Symbol Parameter t Register clear time CLR t PIA delay PIA t Low–power adder LPA Table 15. EPM3064A External Timing Parameters Symbol Parameter t Input to non–registered PD1 output t I/O input to non–registered ...
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... Combinatorial delay COMB t Array clock delay IC t Register enable time EN t Global control delay GLOB t Register preset time PRE t Register clear time CLR Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Conditions –4 Min Max 0.6 0.6 1.8 0.4 1.5 0 ...
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... 1.0 4.9 (2) 2.0 2.0 (3) 2.0 (2) 5.2 (2), (4) 192.3 (2) 5.2 (2), (4) 192.3 Note (1) Speed Grade –7 –10 Max Min Max Min 1.0 1.7 3.5 4.0 Speed Grade –7 –10 Min Max Min 7.5 7.5 4.9 6.6 0.0 0.0 1.0 5.0 1.0 3.0 4.0 3.0 4.0 2.8 3.8 0.3 0.4 1.0 7.1 1.0 3.0 4.0 3.0 4.0 3.0 4.0 7.7 129.9 98.0 7.7 129.9 98.0 Altera Corporation Unit Max 2.3 ns 5.0 ns Unit Max 6 9 10.2 ns MHz 10.2 ns MHz ...
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... Combinatorial delay COMB t Array clock delay IC t Register enable time EN t Global control delay GLOB t Register preset time PRE t Register clear time CLR Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Conditions –5 Min Max 0.7 0.7 2.0 0.4 1.6 0 ...
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... (2) (2) 5.2 (2) 0 1.0 3.0 3.0 (2) 2.7 (2) 0.3 (2) 1.0 3.0 3.0 (3) 3.0 (2) (2), (4) 126.6 (2) (2), (4) 126.6 Note (1) Speed Grade –7 –10 Min Max Min Max 2.0 2.6 4.0 5.0 Speed Grade –10 Max Min Max 7.5 10 7.5 10 6.9 0.0 4.8 1.0 6.4 4.0 4.0 3.6 0.5 7.3 1.0 9.7 4.0 4.0 4.0 7.9 10.5 95.2 7.9 10.5 95.2 Altera Corporation Unit ns ns Unit MHz ns MHz ...
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... Global control delay GLOB t Register preset time PRE t Register clear time CLR t PIA delay PIA t Low–power adder LPA Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Note (1) Conditions 3 2 (2) ...
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... Min Max (2) 7 (2) 7.5 (2) 5.6 (2) 0.0 3.0 0 1.0 4.7 3.0 3.0 (2) 2.5 (2) 0 (2) 1.0 7.8 3.0 3.0 (3) 3.0 (2) 8.6 (2), (4) 116.3 (2) 8.6 (2), (4) 116.3 Note (1) Conditions Speed Grade -7 Min Max 0.7 0.7 3.1 Unit -10 Min Max 10.0 ns 10.0 ns 7.6 ns 0.0 ns 3.0 ns 0.0 ns 1.0 6.3 ns 4.0 ns 4.0 ns 3.5 ns 0.3 ns 1.0 10.4 ns 4.0 ns 4.0 ns 4.0 ns 11.5 ns 87.0 MHz 11.5 ns 87.0 MHz Unit -10 Min Max 0.9 ns 0.9 ns 3.6 ns Altera Corporation ...
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... Array clock delay IC t Register enable time EN t Global control delay GLOB t Register preset time PRE t Register clear time CLR t PIA delay PIA Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Note (1) Conditions Speed Grade -7 Min Max 2.7 0.4 2.2 1 ...
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... Max Min 4.5 Table 10 on page parameter into the signal LAD , and t parameters for macrocells SEXP ACL CPPW , in MHz) for MAX 3000A MAX + Devices). – TON USED equation are: Unit Max 5.0 ns 19. See parameter LPA f tog ) MAX LC Altera Corporation ...
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... Average percentage of logic cells toggling at each clock tog LC (typically 12.5 Constants (shown in Table 23. MAX 3000A I Equation Constants CC Device EPM3032A EPM3064A EPM3128A EPM3256A EPM3512A The I calculation provides an I CCINT conditions using a pattern of a 16–bit, loadable, enabled, up/down counter in each LAB with no output load. Actual I during operation because this measurement is sensitive to the actual pattern in the device and the environmental operating conditions ...
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... MAX 3000A Programmable Logic Device Family Data Sheet Figure 12 vs. Frequency for MAX 3000A Devices CC EPM3032A Room Temperature High Speed Typical Active (mA EPM3064A Room Temperature 140 120 100 High Speed Typical I CC Active (mA) ...
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... Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Figure 13. I vs. Frequency for MAX 3000A Devices CC EPM3128A 210 180 150 Typical I CC 120 Active (mA EPM3256A 350 300 250 Typical I CC 200 Active (mA) 150 100 50 0 EPM3512A 600 500 ...
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... PLCC 38 through 18 show the package pin–out diagrams for Pin 1 39 I/O I/O/TDI 38 I/O/TDO I/O 37 I/O I/O 36 GND GND 35 VCC I/O 34 I/O I/O 33 I/O I/O/TMS 32 I/O/TCK I/O 31 I/O VCC 30 GND 29 I/O I/O GND Pin 12 Pin 34 I/O I/O/TDO I/O GND VCC EPM3032A I/O EPM3064A I/O I/O/TCK I/O GND I/O Pin 23 44-Pin TQFP Altera Corporation ...
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... Figure 15. 100–Pin TQFP Package Pin–Out Diagram Package outline not drawn to scale. Figure 16. 144–Pin TQFP Package Pin–Out Diagram Package outline not drawn to scale Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Pin 1 EPM3064A EPM3128A Pin 26 . Indicates location ...
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... MAX 3000A Programmable Logic Device Family Data Sheet Figure 17. 208–Pin PQFP Package Pin–Out Diagram Package outline not drawn to scale Pin 1 Pin EPM3256A EPM3512A Pin 157 Pin 105 Altera Corporation ...
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... Indicates Location of Ball A1 EPM3512A Revision History Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet . The information contained in the MAX 3000A Programmable Logic Device Data Sheet version 3.2 supersedes information published in previous versions. The following changes were made in the MAX 3000A Programmable Logic Device Data Sheet version 3 ...
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... Device Data Sheet version 3.0: 101 Innovation Drive San Jose, CA 95134 Copyright © 2002 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the (408) 544-7000 stylized Altera logo, specific device designations, and all other words and logos that are identified as http://www ...