EPM570F256C4N Altera, EPM570F256C4N Datasheet - Page 9
![IC MAX II CPLD 570 LE 256-FBGA](/photos/6/70/67063/544-256-fbga_sml.jpg)
EPM570F256C4N
Manufacturer Part Number
EPM570F256C4N
Description
IC MAX II CPLD 570 LE 256-FBGA
Manufacturer
Altera
Series
MAX® IIr
Specifications of EPM570F256C4N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
5.4ns
Voltage Supply - Internal
2.5V, 3.3V
Number Of Logic Elements/blocks
570
Number Of Macrocells
440
Number Of I /o
160
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
256-FBGA
Voltage
2.5V, 3.3V
Memory Type
FLASH
Number Of Logic Elements/cells
570
No. Of I/o's
160
Propagation Delay
7ns
Global Clock Setup Time
1.5ns
Frequency
247.5MHz
Supply Voltage Range
2.375V To 2.625V, 3V To 3.6V
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
No. Of Macrocells
440
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
544-1313
EPM570F256C4N
EPM570F256C4N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM570F256C4N
Manufacturer:
ALTERA
Quantity:
50
Part Number:
EPM570F256C4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Introduction
Functional Description
© October 2008 Altera Corporation
MII51002-2.2
This chapter describes the architecture of the MAX II device and contains the
following sections:
■
■
■
■
■
■
■
■
MAX
implement custom logic. Row and column interconnects provide signal interconnects
between the logic array blocks (LABs).
The logic array consists of LABs, with 10 logic elements (LEs) in each LAB. An LE is a
small unit of logic providing efficient implementation of user logic functions. LABs
are grouped into rows and columns across the device. The MultiTrack interconnect
provides fast granular timing delays between LABs. The fast routing between LEs
provides minimum timing delay for added levels of logic versus globally routed
interconnect structures.
The MAX II device I/O pins are fed by I/O elements (IOE) located at the ends of LAB
rows and columns around the periphery of the device. Each IOE contains a
bidirectional I/O buffer with several advanced features. I/O pins support Schmitt
trigger inputs and various single-ended standards, such as 66-MHz, 32-bit PCI, and
LVTTL.
MAX II devices provide a global clock network. The global clock network consists of
four global clock lines that drive throughout the entire device, providing clocks for all
resources within the device. The global clock lines can also be used for control signals
such as clear, preset, or output enable.
“Functional Description” on page 2–1
“Logic Array Blocks” on page 2–4
“Logic Elements” on page 2–6
“MultiTrack Interconnect” on page 2–12
“Global Signals” on page 2–16
“User Flash Memory Block” on page 2–18
“MultiVolt Core” on page 2–22
“I/O Structure” on page 2–23
®
II devices contain a two-dimensional row- and column-based architecture to
2. MAX II Architecture
MAX II Device Handbook