EPM570F256C4N Altera, EPM570F256C4N Datasheet - Page 31
![IC MAX II CPLD 570 LE 256-FBGA](/photos/6/70/67063/544-256-fbga_sml.jpg)
EPM570F256C4N
Manufacturer Part Number
EPM570F256C4N
Description
IC MAX II CPLD 570 LE 256-FBGA
Manufacturer
Altera
Series
MAX® IIr
Specifications of EPM570F256C4N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
5.4ns
Voltage Supply - Internal
2.5V, 3.3V
Number Of Logic Elements/blocks
570
Number Of Macrocells
440
Number Of I /o
160
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
256-FBGA
Voltage
2.5V, 3.3V
Memory Type
FLASH
Number Of Logic Elements/cells
570
No. Of I/o's
160
Propagation Delay
7ns
Global Clock Setup Time
1.5ns
Frequency
247.5MHz
Supply Voltage Range
2.375V To 2.625V, 3V To 3.6V
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
No. Of Macrocells
440
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
544-1313
EPM570F256C4N
EPM570F256C4N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM570F256C4N
Manufacturer:
ALTERA
Quantity:
50
Part Number:
EPM570F256C4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Chapter 2: MAX II Architecture
I/O Structure
I/O Structure
Fast I/O Connection
© October 2008 Altera Corporation
IOEs support many features, including:
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MAX II device IOEs contain a bidirectional I/O buffer.
IOE structure. Registers from adjacent LABs can drive to or be driven from the IOE’s
bidirectional I/O buffers. The Quartus II software automatically attempts to place
registers in the adjacent LAB with fast I/O connection to achieve the fastest possible
clock-to-output and registered output enable timing. For input registers, the
Quartus II software automatically routes the register to guarantee zero hold time.
You can set timing assignments in the Quartus II software to achieve desired I/O
timing.
A dedicated fast I/O connection from the adjacent LAB to the IOEs within an I/O
block provides faster output delays for clock-to-output and t
This connection exists for data output signals, not output enable signals or input
signals.
LVTTL and LVCMOS I/O standards
3.3-V, 32-bit, 66-MHz PCI compliance
Joint Test Action Group (JTAG) boundary-scan test (BST) support
Programmable drive strength control
Weak pull-up resistors during power-up and in system programming
Slew-rate control
Tri-state buffers with individual output enable control
Bus-hold circuitry
Programmable pull-up resistors in user mode
Unique output enable per pin
Open-drain outputs
Schmitt trigger inputs
Fast I/O connection
Programmable input delay
Figure
2–20,
Figure
2–21, and
Figure 2–22
illustrate the fast I/O connection.
Figure 2–19
PD
propagation delays.
shows the MAX II
MAX II Device Handbook
2–23