XCR3256XL-12TQ144C Xilinx Inc, XCR3256XL-12TQ144C Datasheet - Page 12

• Manufacturer Part Number: XCR3256XL-12TQ144C
• Description: IC CR CPLD 6K 256MCELL 144-TQFP
• Manufacturer: Xilinx Inc
• Series: CoolRunner XPLA3r

Specifications of XCR3256XL-12TQ144C

• Programmable Type: In System Programmable (min 1K program/erase cycles)
• Delay Time Tpd(1) Max: 10.8ns
• Voltage Supply - Internal: 3 V ~ 3.6 V
• Number Of Logic Elements/blocks: 16
• Number Of Macrocells: 256
• Number Of Gates: 6000
• Number Of I /o: 120
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-TQFP, 144-VQFP
• Voltage: 3.3V
• Memory Type: EEPROM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -
• Other names: 122-1283

XCR3256XL 256 Macrocell CPLD
Warranty Disclaimer
THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED
AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE
PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE
THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE
AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF
LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
Additional Information
CoolRunner XPLA3 Data Sheets and Application Notes
Device Package User Guide
Revision History
The following table shows the revision history for this document
12
Notes:
1.
XCR3256XL-12FT256C
XCR3256XL-12CS280C
XCR3256XL-12CSG280C
XCR3256XL-12TQ144I
XCR3256XL-12TQG144I
XCR3256XL-12PQ208I
XCR3256XL-12PQG208I
XCR3256XL-12FT256I
XCR3256XL-12CS280I
XCR3256XL-12CSG280I
Part Marking Number
Device Ordering and
01/21/00
02/10/00
05/03/00
11/20/00
12/11/00
01/17/01
03/05/01
04/11/01
04/19/01
C = Commercial: T
Date
Version
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
A
= 0° to +70°C; I = Industrial: T
(pin-to-pin
Initial Xilinx release.
Updated Pinout table.
Minor updates and added Boundary Scan to pinout table.
Updated pinout tables; corrected note in
Updated specifications and pinout tables.
Removed Timing Model.
Added 256-ball Fine-Pitch Ball Grid Array Package.
Added Typical I/V curve,
Updated Typical I/V curve,
Speed
delay)
12 ns
12 ns
12 ns
12 ns
12 ns
12 ns
12 ns
12 ns
12 ns
12 ns
CSG280 280-ball
TQG144 144-pin
PQG208 208-pin
CSG280 280-ball
Symbol
CS280
TQ144
PQ208
CS280
FT256
FT256
Pkg.
A
= –40° to +85°C
256-ball
280-ball
256-ball
280-ball
144-pin
208-pin
www.xilinx.com
No. of
Pins
Figure
Figure
2; added
Device Packages
2: added voltage levels.
Plastic Quad Flat Pack (PQFP); Pb-Free
Thin Quad Flat Pack (TQFP); Pb-Free
Chip Scale Package (CSP); Pb-Free
Chip Scale Package (CSP); Pb-Free
Plastic Quad Flat Pack (PQFP)
Revision
Thin Quad Flat Pack (TQFP)
Table 4
Chip Scale Package (CSP)
Chip Scale Package (CSP)
Table
Fine-Pitch BGA (FT)
Fine-Pitch BGA (FT)
Package Type
2: Total User I/O; changed V
to read: "port enable pin is brought High".
DS013 (v2.7) March 31, 2006
Product Specification
OH
spec.
Operating
Range
C
C
C
I
I
I
I
I
I
I
(1)
R