EPM9320LC84-15 Altera, EPM9320LC84-15 Datasheet - Page 12

• Manufacturer Part Number: EPM9320LC84-15
• Description: IC MAX 9000 CPLD 320 84-PLCC
• Manufacturer: Altera
• Series: MAX® 9000r

Specifications of EPM9320LC84-15

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 15.0ns
• Voltage Supply - Internal: 4.75 V ~ 5.25 V
• Number Of Logic Elements/blocks: 20
• Number Of Macrocells: 320
• Number Of Gates: 6000
• Number Of I /o: 60
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Voltage: 3.3V/5V
• Memory Type: EEPROM
• Number Of Logic Elements/cells: 20
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 544-2362-5

MAX 9000 Programmable Logic Device Family Data Sheet
12
The MAX+PLUS II Compiler automatically allocates as many as three sets
of up to five parallel expanders to macrocells that require additional
product terms. Each set of expanders incurs a small, incremental timing
delay (t
Compiler uses the five dedicated product terms within the macrocell and
allocates two sets of parallel expanders; the first set includes five product
terms and the second set includes four product terms, increasing the total
delay by 2 t
Two groups of eight macrocells within each LAB (e.g., macrocells 1
through 8 and 9 through 16) form two chains to lend or borrow parallel
expanders. A macrocell borrows parallel expanders from lower-
numbered macrocells. For example, macrocell 8 can borrow parallel
expanders from macrocell 7, from macrocells 7 and 6, or from macrocells
7, 6, and 5. Within each group of 8, the lowest-numbered macrocell can
only lend parallel expanders and the highest-numbered macrocell can
only borrow them.
FastTrack Interconnect
In the MAX 9000 architecture, connections between macrocells and device
I/O pins are provided by the FastTrack Interconnect, a series of
continuous horizontal and vertical routing channels that traverse the
entire device. This device-wide routing structure provides predictable
performance even in complex designs. In contrast, the segmented routing
in FPGAs requires switch matrices to connect a variable number of
routing paths, increasing the delays between logic resources and reducing
performance.
with row and column interconnects.
PEXP
). For example, if a macrocell requires 14 product terms, the
PEXP
Figure 6
.
shows the interconnection of four adjacent LABs
Altera Corporation