EPM240GM100C5N Altera, EPM240GM100C5N Datasheet - Page 2

• Manufacturer Part Number: EPM240GM100C5N
• Description: IC MAX II CPLD 240 LE 100-MBGA
• Manufacturer: Altera
• Series: MAX® IIr

Specifications of EPM240GM100C5N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 4.7ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 240
• Number Of Macrocells: 192
• Number Of I /o: 80
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-MBGA
• Voltage: 1.8V
• Memory Type: FLASH
• Number Of Logic Elements/cells: 240
• Family Name: MAX II
• # Macrocells: 192
• Frequency (max): 1.8797GHz
• Propagation Delay Time: 7.5ns
• Number Of Logic Blocks/elements: 24
• # I/os (max): 80
• Operating Supply Voltage (typ): 1.8V
• In System Programmable: Yes
• Operating Supply Voltage (min): 1.71V
• Operating Supply Voltage (max): 1.89V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: MBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1726

MAX II Device Family
MAX II Power-up
Issue
2
Preliminary
Notes to
(1)
(2)
(3)
EPM1270 engineering sample (ES)
devices are not compatible with
EPM1270 production device
Programming Object Files (.pof).
MAX II (3.3V V
MAX II (2.5V V
Table 1. MAX II Device Family Issues (Continued)
Table 2. Recommended V
Device and VCCINT Operating
See the
Altera is offering permanent recommendations and workarounds for this issue.
This issue is a permanent programming file compatibility restriction.
Table
“MAX II Power-up
Voltage
1:
CCINT
CCINT
Issue
)
)
CCINT
The MAX II devices may not power-up and enter user mode correctly for
either of the following conditions:
1. V
2. V
voltage regions shown in
This power-up issue is only affected by the V
times or profiles do not affect the MAX II device behavior for this issue.
This issue affects all MAX II devices shown in
The failed power-up condition results in all I/O pins remaining tri-state
with weak pull-up resistors even though V
While in this state, the JTAG port is unresponsive for programming or
boundary scan operations. User mode operation does not begin unless
V
To ensure successful power-up, Altera recommends (as shown in
that you provide a sufficient rise time with a monotonic V
profile that contains no dips within the voltage windows.
Issue”section for information on distinguishing revision codes.
CCINT
Rise Times and V
CCINT
CCINT
EPM1270 ES Devices
power to the MAX II device is recycled.
Recommended V
rise profile exhibits any non-monotonic dips or noise within the
rises slower than the times shown in
Affected Devices
<= 750 µs
<= 1.0 ms
CCINT
(1)
Noise/Dip Free Window
CCINT
Table
Rise Time
2.
(3)
Recommended POR Dip/Noise
CCINT
CCINT
Table
Table
has been fully powered.
Fixed Devices
Free Window
supply; V
1.
1.5-1.8V
1.5-1.8V
2.
Altera Corporation
CCINT
CCIO
rise
Table
rise
2)