ATF1508RE-7AU100 Atmel, ATF1508RE-7AU100 Datasheet - Page 8
![IC CPLD EE 128MC 5NS 100-TQFP](/photos/6/70/67048/313-100-tqfp_sml.jpg)
ATF1508RE-7AU100
Manufacturer Part Number
ATF1508RE-7AU100
Description
IC CPLD EE 128MC 5NS 100-TQFP
Manufacturer
Atmel
Series
ATF1508REr
Specifications of ATF1508RE-7AU100
Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Macrocells
128
Number Of I /o
80
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Features
Programmable
Voltage
1.8V, 2.5V, 3.3V
Memory Type
EEPROM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Logic Elements/cells
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
1.6
1.7
2. Input and I/O Pins
2.1
8
Global Bus/Switch Matrix
Foldback Bus
Programmable Pin-keeper Option for Inputs and I/Os
ATF1508RE
The global bus contains all input and I/O pin signals as well as the buried feedback signal from
all 128 macrocells. The switch matrix in each logic block receives as its inputs all signals from
the global bus. Under software control, up to 40 of these signals can be selected as inputs to the
logic block.
Each macrocell also generates a foldback product term. This signal goes to the regional bus and
is available to all 16 macrocells within the logic block. The foldback is an inverse polarity of one
of the macrocell’s product terms. The 16 foldback terms in each logic block allow generation of
high fan-in sum terms or other complex logic functions with little additional delay.
The ATF1508RE offers the option of individually programming each of its input or I/O pin so that
pin-keeper circuit can be utilized. When any pin is driven high or low and then subsequently left
floating, it will stay at that previous high or low level. This circuitry prevents undriven input and
I/O lines from floating to intermediate voltage levels, which causes unnecessary power con-
sumption and system noise. The keeper circuits eliminate the need for external pull-up resistors
and eliminate their DC power consumption.
Figure 2-1
I/O pin. The pin-keeper circuit is a weak feedback latch and has an effective resistance that is
approximately 50 kΩ.
Figure 2-1.
shows the pin-keeper circuit for an Input Pin and
Input with Programmable Pin-keeper
50K
Figure 2-2
V
CCINT
shows the same for an
3682A–PLD–10/08