AD1854JRS Analog Devices Inc, AD1854JRS Datasheet
AD1854JRS
Specifications of AD1854JRS
Available stocks
Related parts for AD1854JRS
AD1854JRS Summary of contents
Page 1
FEATURES 5 V Stereo Audio DAC System Accepts 16-/18-/20-/24-Bit Data Supports 24 Bits and 96 kHz Sample Rate Multibit Sigma-Delta Modulator with “Perfect Differential Linearity Restoration” for Reduced Idle Tones and Noise Floor Data Directed Scrambling DAC—Least Sensitive to ...
Page 2
... Dynamic Range ( kHz, –60 dB Input) No Filter (AD1854JRS) No Filter (AD1854KRS) With A-Weighted Filter (AD1854JRS) With A-Weighted Filter (AD1854KRS) Total Harmonic Distortion + Noise (AD1854JRS) V Total Harmonic Distortion + Noise (AD1854KRS) V Total Harmonic Distortion + Noise (AD1854JRS and AD1854KRS – Total Harmonic Distortion + Noise (AD1854JRS and AD1854KRS –60 dB ...
Page 3
POWER Supplies Voltage, Analog and Digital Analog Current Analog Current—Power-Down Digital Current Digital Current—Power-Down Dissipation Operation—Both Supplies Operation—Analog Supply Operation—Digital Supply Power-Down—Both Supplies Power Supply Rejection Ratio 1 kHz 300 mV p-p Signal at Analog Supply Pins 20 kHz 300 ...
Page 4
... Resistance JC [Junction-to-Case]) Model Temperature AD1854JRS 0°C to 70°C AD1854JRSRL 0°C to 70°C AD1854KRS 0°C to 70°C AD1854KRSRL 0°C to 70°C CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. ...
Page 5
Pin Input/Output Pin Name 1 I DGND 2 I MCLK 3 I CLATCH 4 I CCLK 5 I CDATA 6 I 384/256 7 I X2MCLK 8 O ZEROR 9 I DEEMP 10 I 96/48 11 AGND 12 O ...
Page 6
AD1854 OPERATING FEATURES Serial Data Input Port The AD1854’s flexible serial data input port accepts data in twos-complement, MSB-first format. The left channel data field always precedes the right channel data field. The input data consists of either 16, 18, ...
Page 7
L/RCLK LEFT CHANNEL INPUT BCLK INPUT SDATA MSB MSB–1 MSB–2 INPUT L/RCLK LEFT CHANNEL INPUT BCLK INPUT SDATA LSB MSB MSB–1 MSB–2 INPUT t CCP CDATA D15 CCLK t CCH t CCL CLATCH Serial Control Port The AD1854 serial control ...
Page 8
AD1854 CLATCH CCLK CDATA 20 40 CLATCH CCLK CDATA 200 400 Burst Mode To operate with SPI CCLK frequencies up to 12.288 MHz, the SPI port can be operated in Burst Mode. This means that when CLATCH is high, CCLK ...
Page 9
Timing Diagrams The serial data port timing is shown in Figures 9 and 10. The minimum bit clock HI pulsewidth is t DBH clock LO pulsewidth The minimum bit clock period is DBL t . The left/right ...
Page 10
... OUTL– C14 1nF, NP0 384/256 C13 X2MCLK 1nF, NP0 R17 1.96k SDATA OUTL+ L/RCLK 2.15k BCLK U1 AD1854JRS MCLK IDPM0 R13 R18 2.15k IDPM1 1.96k OUTR– DEEMP C17 1nF, NP0 MUTE C16 CLATCH 1nF, NP0 R19 1.96k ...
Page 11
TYPICAL PERFORMANCE Figures 13 through 20 illustrate the typical analog performance of the AD1854 as measured by an Audio Precision System Two. Signal-to-Noise and THD+N performance are shown under a range of conditions. Figure 14 shows the power supply rejection ...
Page 12
AD1854 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 100 FREQUENCY – kHz Figure 19. Digital Filter Response 0.32 (8.20) 0.29 (7.40) 0.079 (2.0) MAX (0.05) 0 –10 –20 –30 –40 –50 ...