MT9075BP1 Zarlink, MT9075BP1 Datasheet - Page 81

• Manufacturer Part Number: MT9075BP1
• Description: PB FREE E1 SINGLE CHIP TRANSCEIVER
• Manufacturer: Zarlink

Bit
7
6
5
4
3
2
1
0
RTloop
Name
HRST
(0000
0000)
RSV
RSV
RSV
RSV
Ftst
(0)
(0)
(0)
(0)
(0)
(0)
---
Table 95 - HDLC Test Control Register
HDLC Reset. When this bit is set to one, the HDLC will be reset. This is
similar to RESET being applied, the only difference being that this bit will
not be reset automatically. This bit can only be reset by writing a zero twice
to this location or applying RESET.
RT Loopback. When this bit is set to one, receive to transmit HDLC
loopback will be activated. Receive data, including end of packet indication,
but not including flags or CRC, will be written to the TX FIFO as well as the
RX FIFO. When the transmitter is enabled, this data will be transmitted as
though written by the microprocessor. Both good and bad packets will be
looped back. Receive to transmit loopback may also be accomplished by
reading the RX FIFO using the microprocessor and writing these bytes,
with appropriate tags, into the TX FIFO.
Reserved; must be set to 0 for normal operation.
Reserved; must be set to 0 for normal operation.
Reserved; must be set to 0 for normal operation.
FIFO Test. This bit when set to one allows the writing to the RX FIFO and
reading of the TX FIFO through the microprocessor to allow more efficient
testing of the FIFO status/interrupt functionality. This is done by making a
TX FIFO write become a RX FIFO write and a RX FIFO read become a TX
FIFO read. In addition, EOP/FA and RQ8/RQ9 are re-defined to be
accessible (i.e. RX write causes EOP/FA to go to RX fifo input; TX read
looks at output of TX FIFO through RQ8/RQ9 bits).
Reserved; must be set to 0 for normal operation.
Unused.
(Pages 0BH & 0CH, Address 1BH)
Zarlink Semiconductor Inc.
MT9075B
81
Functional Description
Data Sheet