MT9075BP1 Zarlink, MT9075BP1 Datasheet - Page 79

• Manufacturer Part Number: MT9075BP1
• Description: PB FREE E1 SINGLE CHIP TRANSCEIVER
• Manufacturer: Zarlink

7 - 0
Bit
Bit
7
6
5
4
3
2
1
0
FA: Txunder
Crc15-8
RxOvfl
EOPD
EOPR
Name
TEOP
Name
TxFL
RxFf
GA
Table 91 - HDLC Interrupt Status Register
Table 92 - Receive CRC MSB Register
Go-Ahead. Indicates a go-ahead pattern was detected by the HDLC
receiver. This bit is reset after a read.
End Of Packet Detect. This bit is set to one when an end of packet (EOP)
byte was written into the RX FIFO by the HDLC receiver. This can be in
the form of a flag, an abort sequence or as an invalid packet. This bit is
reset after a read.
Transmit End Of Packet. This bit is set to one when the transmitter has
finished sending the closing flag of a packet or after a packet has been
aborted. This bit is reset after read.
End Of Packet Read. This bit is set to one when the byte about to be read
from the RX FIFO is the last byte of the packet. It is also set to one if the
Rx FIFO is read and there is no data in it. This bit is reset after a read.
TX FIFO Low. This bit is set to one when the TX FIFO is emptied below
the selected low threshold level. This bit is reset after a read.
Frame Abort/TX FIFO Underrun. When Intsel bit of Control Register 2 is
low, this bit is set to one when a frame abort is received during packet re-
ception. It must be received after a minimum number of bits have been re-
ceived (26) otherwise it is ignored.
When Intsel bit of Control Register 2 is one, this bit is set to one for a TX
FIFO underrun indication. If one it indicates that a read by the transmitter
was attempted on an empty Tx FIFO.
This bit is reset after a read.
RX FIFO Full. This bit is set to one when the RX FIFO is filled above the
selected full threshold level. This bit is reset after a read.
RX FIFO Overflow. A one indicates that the 128 byte RX FIFO
overflowed (i.e. an attempt to write to a 128 byte full RX FIFO). The HDLC
will always disable the receiver once the receive overflow has been
detected. The receiver will be re-enabled upon detection of the next flag,
but will overflow again unless the RX FIFO is read. This bit is reset after a
read.
The MSB byte of the CRC received from the transmitter. These bits are
as the transmitter sent them; that is, most significant bit first and inverted.
This register is updated at the end of each received packet and therefore
should be read when end of packet is detected.
(Page 0BH & 0CH, Address 17H)
(Pages 0BH & 0CH, Address 18H)
Zarlink Semiconductor Inc.
MT9075B
79
Functional Description
Functional Description
Data Sheet