MT9075BP1 Zarlink, MT9075BP1 Datasheet - Page 20

• Manufacturer Part Number: MT9075BP1
• Description: PB FREE E1 SINGLE CHIP TRANSCEIVER
• Manufacturer: Zarlink

Note that the Data Link (DL) pin functions, if selected, override the transmit national bit buffer function.
The CRC-4 Alignment status CALN (page 03H, address 12H) and maskable interrupt CALNI (page 01H, address
1DH) indicate the beginning of every received CRC-4 multiframe.
Maskable interrupts are available for change of state of S
proper control bits, an interrupt can be generated on a change of state of any S
for the data link), or any nibbles for S
In addition, the transparent transmission of channel 0 is supported to meet the ETS requirement. Selectable on a bit
by bit basis, S
transparently onto the line.
Data Link Operation
Timeslot 0
The MT9075B has a user defined 4, 8, 12, 16 or 20 kbit/s data link for transport of maintenance and performance
monitoring information across the PCM 30 link. This channel functions using the S
timeslot zero non-frame alignment signal (NFAS). Since the NFAS is transmitted every other frame - a periodicity of
250 microseconds - the aggregate bit rate is a multiple of 4 kb/s. As there are five S
for this data link, the bit rate will be 4, 8, 12, 16 or 20 kb/s, depending on the bits selected for the Data Link (DL).
The S
Word (page 01H, address 10H, bits 4-0). Access to the DL is provided by pins TxDLCLK, TxDL, RxDLCLK and
RxDL, which allow easy interfacing to an external controller.
Data to be transmit onto the line in the S
MQFP) with the clock TxDLCLK (pin 64 in PLCC, pin 61 in MQFP). Although the aggregate clock rate equals the bit
rate, it has a nominal pulse width of 244 ns, and it clocks in the TxDL as if it were a 2.048 Mb/s data stream. The
clock can only be active during bit times 4 to 0 of the STBUS frame. The TxDL input signal is clocked into the
MT9075B by the rising edge of TxDLCLK. If bits are selected to be a part of the DL, all other programmed functions
for those S
The RxDLCLK signal (pin 39 in PLCC, pin 20 in MQFP) is derived from the receive extracted clock and is
aligned with the receive data link output RxDL. The HDB3 decoded receive data, at 2.048 Mbit/s, is clocked out
a
bits used for the DL are selected by setting the appropriate bits, S
a
bit positions are overridden.
a
bits in channel 0 DSTi data can be programmed using register 17H of page 01H to be sent
Byte
ress
Add
able
NB
NB
NB
NB
NB
B0
B1
B2
B3
B4
s
Table 8 - MT9075B National Bit Buffers
a5
Frames 1, 3, 5, 7, 9, 11, 13 & 15 of a CRC-4
S
S
S
S
S
F1
through S
a4
a5
a6
a7
a8
a
bit position is clocked in from the TxDL pad (pin 65 in PLCC, pin 62 in
S
S
S
S
S
F3
a4
a5
a6
a7
a8
Zarlink Semiconductor Inc.
a8
S
S
S
S
S
MT9075B
F5
. See the description of page 01H, address 19H for more details.
a4
a5
a6
a7
a8
Multiframe
20
S
S
S
S
S
F7
a4
a5
a6
a7
a8
a5
bits or change of state of S
S
S
S
S
S
F9
a4
a5
a6
a7
a8
S
S
S
S
S
F1
1
a4
a5
a6
a7
a8
S
S
S
S
S
F1
3
a4
a5
a6
a7
a8
a4
~S
a
S
S
S
S
S
F1
bit (except S
a8
5
a4
a5
a6
a7
a8
, to one in the Data Link Select
a
a
bits (S
bits independently available
a6
a4
nibbles. By writing the
a4
~S
- normally reserved
a8
) of the PCM 30
Data Sheet