K6R4016V1D-UI10T00 SAMSUNG, K6R4016V1D-UI10T00 Datasheet - Page 8

• Manufacturer Part Number: K6R4016V1D-UI10T00
• Manufacturer: SAMSUNG

K6R4016V1D
TIMING WAVEFORM OF WRITE CYCLE(1)
TIMING WAVEFORM OF WRITE CYCLE(2)
OE
Address
CS
UB, LB
WE
Data in
Data out
Address
CS
UB, LB
WE
Data in
Data out
NOTES(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. t
4. At any given temperature and voltage condition, t
5. Transition is measured 200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=V
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
levels.
device.
HZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V
High-Z
High-Z
t
t
AS(4)
AS(4)
(OE Clock)
(OE=Low fixed)
IL.
PRELIMPreliminaryPPPPPPPPPINARY
t
OHZ(6)
- 8 -
HZ
t
t
(Max.) is less than t
WHZ(6)
AW
t
CW(3)
t
t
t
AW
t
WC
WC
t
CW(3)
BW
t
BW
t
WP(2)
t
WP1(2)
LZ
t
High-Z
DW
(Min.) both for a given device and from device to
t
DW
Valid Data
Valid Data
t
WR(5)
t
WR(5)
t
DH
t
DH
t
OW
CMOS SRAM
High-Z
(10)
Mar. 2004
OH
Rev 4.0
(9)
or V
OL