GS8662Q18GE-250 GSI TECHNOLOGY, GS8662Q18GE-250 Datasheet - Page 22

• Manufacturer Part Number: GS8662Q18GE-250
• Manufacturer: GSI TECHNOLOGY

AC Electrical Characteristics (Continued)
Rev: 1.08 12/2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Hold Times
Address Input Hold Time
Control Input Hold Time
Data Input Hold Time
Notes:
1.
2.
3.
4.
5.
6.
7.
All Address inputs must meet the specified setup and hold times for all latching clock edges.
Control singles are R, W, BW0, BW1, and (NW0, NW1 for x8) and (BW2, BW3 for x36).
If C, C are tied high, K, K become the references for C, C timing parameters
To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN
parameter that is worst case at totally different test conditions (0°C, 1.9 V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7 V). It is not possible for two
SRAMs on the same board to be at such different voltages and temperatures.
Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
V
Echo clock is very tightly controlled to data valid/data hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheet parameters reflect tester guard
bands and test setup variations.
DD
slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once V
Parameter
Symbol
t
t
t
KHAX
KHDX
KHIX
Min
0.3
0.3
0.3
-278
22/35
Max
—
—
—
Min
0.35
0.35
0.35
-250
Max
—
—
—
GS8662Q08/09/18/36E-278/250/200/167
DD
Min
0.4
0.4
0.4
and input clock are stable.
-200
Max
—
—
—
Min
0.5
0.5
0.5
-167
Max
—
—
—
© 2005, GSI Technology
Units
ns
ns
ns
Notes