MAX5541CSA+T Maxim Integrated Products, MAX5541CSA+T Datasheet - Page 6

• Manufacturer Part Number: MAX5541CSA+T
• Description: IC DAC 16BIT MONOTONIC SER 8SOIC
• Manufacturer: Maxim Integrated Products

Specifications of MAX5541CSA+T

• Settling Time: 1µs
• Number Of Bits: 16
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 1.5mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX5541 voltage-output, 16-bit digital-to-analog
converter (DAC) offers 16-bit monotonicity with less
than 1LSB differential linearity error. Serial-data transfer
minimizes the number of package pins required.
The MAX5541 is composed of two matched DAC sec-
tions, with a 12-bit inverted R-2R DAC forming the
twelve LSBs and the four MSBs derived from fifteen
identically matched resistors. This architecture allows
the lowest glitch energy to be transferred to the DAC
output on major-carry transitions. It also decreases the
DAC output impedance by a factor of eight compared
to a standard R-2R ladder, allowing unbuffered opera-
tion in medium-load applications. Figure 1 is the Timing
Diagram.
The MAX5541 digital interface is a standard 3-wire con-
nection compatible with SPI/QSPI/MICROWIRE inter-
faces. The chip-select input (CS) frames the serial data
loading at the data input pin (DIN). Immediately follow-
ing CSs high-to-low transition, the data is shifted
Low-Cost, +5V, Serial-Input,
Voltage-Output, 16-Bit DAC
6
Figure 1. Timing Diagram
Figure 2. 3-Wire Interface Timing Diagram
_______________________________________________________________________________________
SCLK
DIN
CS
t
CSHO
SCLK
DIN
CS
Detailed Description
t
CSSO
t
DS
D15
D15
t
DH
D14 D13 D12 D11 D10 D9
MSB
t
CH
Digital Interface
t
CL
D14
D8
D7 D6 D5 D4 D3 D2 D1 D0
synchronously and latched into the input register on the
rising edge of the serial-clock input (SCLK). After 16
data bits have been loaded into the serial input regis-
ter, it transfers its contents to the DAC latch on CSs
low-to-high transition (Figure 2). Note that if CS does
not remain low during the entire sixteen SCLK cycles,
data will be corrupted. In this case, reload the DAC
latch with a new 16-bit word.
The MAX5541 operates with external voltage refer-
ences from 2V to 3V. The reference voltage determines
the DACs full-scale output voltage.
The MAX5541 has a power-on reset (POR) circuit to set
the DACs output to 0V in unipolar mode when V
first applied. This ensures that unwanted DAC output
voltages will not occur immediately following a system
power-up, such as after power loss. In bipolar mode,
the DAC output is set to -V
D0
LSB
t
CSH1
UPDATED
t
CSS1
DAC
REF
.
External Reference
Power-On Reset
DD
is