PNX1700EH NXP Semiconductors, PNX1700EH Datasheet - Page 298
PNX1700EH
Manufacturer Part Number
PNX1700EH
Description
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1700EH.pdf
(832 pages)
Specifications of PNX1700EH
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / Rohs Status
Not Compliant
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Philips Semiconductors
Volume 1 of 1
Table 10: Sampling and Pattern Generation Control Registers for the FIFO Queues
PNX17XX_SER_1
Preliminary data sheet
Offset 0x10,4024 -> 0x030
31
30
29
28
27:26
25:24
23:22
Bit
Symbol
Unused
EN_EV_TSTAMP
EN_IR_CARRIER
EN_IR_FILTER
EN_CLOCK_SEL
EN_PAT_GEN_CLK
Unused
4.4 Sampling and Pattern Generation Control Registers for the FIFO
Queues
GPIO_EV<0-3>
Acces
s
R/W
R/W
R/W
R/W
R/W
Value
-
0
0
0
0
0
Rev. 1 — 17 March 2006
Description
Enables an event timestamp signal to be generated whenever the
last 32-bit word from a DMA buffer reaches the GPIO output pins.
This field is only valid in Pattern Generating modes, i.e.
FIFO_MODE[1] set to ‘1’.
This bit enables a sub-carrier for Ir transmission. FREQ_DIV[15:0] is
combined with CARRIER_DIV[4:0] to generate sub-carrier and TX
frequencies:
Note: This field is only valid in Pattern Generation using samples
mode (FIFO_MODE=11) with EN_CLOCK_SEL disabled.
This bit enables a received Ir signal to be filtered. No signal pulses
less than the period programmed in IR_FILTER are passed through
to the monitoring logic.
Note: This field is only valid in Signal Sampling mode
(FIFO_MODE=01) with EN_CLOCK_SEL disabled.
Enables an input signal selected by CLOCK_SEL to be used as the
external clock source:
Note: This field is only valid in Signal Sampling mode
(FIFO_MODE=01) and Pattern Generation using samples mode
(FIFO_MODE=11).
Enables the clock generated by the frequency divider to be sent out
of the chip during pattern generation using samples and frequency
divider mode:
Note: This field is only valid in Pattern Generation using samples
(FIFO_MODE=11) and frequency divider (EN_CLOCK_SEL -
disabled) mode
0 - Ir Carrier disabled, CARRIER_DIV[4:0] not used.
1 - Ir Carrier enabled, CARRIER_DIV[4:0] used.
00 - CLOCK_SEL disabled
10 - CLOCK_SEL disabled
01 - CLOCK_SEL enabled, sample on positive edge
11 - CLOCK_SEL enabled, sample on negative edge
00 - EN_PAT_GEN_CLK disabled
10 - EN_PAT_GEN_CLK disabled
01 - EN_PAT_GEN_CLK enabled, output the clock as is
11 - EN_PAT_GEN_CLK enabled, output the inverted clock
Chapter 8: General Purpose Input Output Pins
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
8-27
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