PNX1700EH NXP Semiconductors, PNX1700EH Datasheet - Page 102
PNX1700EH
Manufacturer Part Number
PNX1700EH
Description
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1700EH.pdf
(832 pages)
Specifications of PNX1700EH
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / Rohs Status
Not Compliant
- Current page: 102 of 832
- Download datasheet (8Mb)
Philips Semiconductors
Volume 1 of 1
10. Peripheral Interface
PNX17XX_SER_1
Preliminary data sheet
10.1.1 software I/O
10.1 GPIO - General Purpose Software I/O and Flexible Serial Interface
9.4 Fast General Purpose Output
The Fast General Purpose Output (FGPO) provides data generation capabilities that
match the FGPI:
PNX17xx Series has 16 dedicated GPIO pins. In addition, 45 other pins that have a
high likelihood of not being used in certain applications are designated as optional
GPIO pins that can either operate in regular mode or in GPIO mode. As an example,
some of the data pins of the LAN module are available as fully functional GPIO in
case the system based on PNX17xx Series is not connected to a LAN network
module. The complete list is available in the pin list where a dedicated column defines
the GPIO pin number, see
The GPIO module is connected to many pins. Hence it is the ideal place to provide
useful central system functions. It performs the following major functions, each
detailed below:
Each GPIO pin is a tri-state pin that can be individually enabled, disabled, written or
read. Pins are grouped in groups of 16 and signals within a group can be
simultaneously enabled and changed or observed. Changes can use a mask to allow
certain pins to remain unchanged.
•
•
•
•
•
•
•
In combination with VDI_MODE[7] bit, see
basic Video In module by storing in memory at specific locations the different
lines and fields of the in-coming video data. Note that the YUV data is stored
consecutively in memory and not stored in three different planes.
generation of a structured data stream, indicating record and buffer start over two
control wires. Generated data can be 8-, 16- or 32-bit wide, with data rates up to
108 MHz at respectively 100, 200 and 432 MB/s.
message passing (8-, 16- or 32-bit wide)
External synchronization available
software I/O - set a pin or pin group, enable a pin (group), inspect pin values
precise timestamping of internal and external events (up to 12 signals
simultaneously)
signal event sequence monitoring or signal generation (up to 4 signals
simultaneously)
Rev. 1 — 17 March 2006
Section 2.3 on page
Section
1-3.
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
9.1, FGPI can be used as a
PNX17xx Series
Chapter 2: Overview
2-21
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