TC59LM818DMBI-37 Toshiba, TC59LM818DMBI-37 Datasheet - Page 32

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TC59LM818DMBI-37

Manufacturer Part Number
TC59LM818DMBI-37
Description
Manufacturer
Toshiba
Type
DDR FCRAMr
Datasheet

Specifications of TC59LM818DMBI-37

Organization
16Mx18
Density
288Mb
Address Bus
17b
Access Time (max)
650ps
Maximum Clock Rate
533MHz
Operating Supply Voltage (typ)
2.5V
Package Type
BGA
Operating Temp Range
-40C to 100C
Operating Supply Voltage (max)
2.625V
Operating Supply Voltage (min)
2.375V
Supply Current
420mA
Pin Count
60
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Not Compliant
Unidirectional DS/QS mode
Unidirectional DS/Free Running QS mode
Bank Add.
BL = 2
BL = 4
BL = 2
BL = 4
Command
MULTIPLE BANK READ TIMING (CL = 5)
Address
(output)
(output)
(output)
(output)
(output)
(output)
(output)
(output)
(input)
(input)
(input)
(input)
CLK
CLK
DQ
DQ
DQ
DQ
QS
QS
QS
QS
DS
DS
DS
DS
Note: l
Bank
RDA
Low
Hi-Z
Low
Hi-Z
Hi-Z
Hi-Z
UA
"a"
0
I
RBD
RC
= 2 cycles
to the same bank must be satisfied.
LAL
LA
1
I
RC
Bank
RDA
UA
"b"
(Bank"a") = 6 cycles
2
CL = 5
CL = 5
LAL
CL = 5
CL = 5
LA
3
I
RC
4
(Bank"b") = 6 cycles
DESL
CL = 5
CL = 5
CL = 5
CL = 5
5
I
Bank
RDA
RBD
UA
"a"
6
Qa0Qa1
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3
Qa0Qa1
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3
= 2 cycles I
LAL
LA
7
Bank
RDA
UA
"b"
8
Qb0Qb1
RBD
Qb0Qb1
= 2 cycles I
LAL
LA
9
Bank
RDA
UA
10
"c"
RBD
TC59LM818DMBI-37
LAL
11
LA
= 2 cycles I
Bank
RDA
2005-03-07 32/55
UA
12
"d"
Qa0 Qa1
Qa0 Qa1 Qa2 Qa3Qb0Qb1Qb2
Qa0 Qa1 Qa2 Qa3Qb0Qb1Qb2
Qa0 Qa1
RBD
LAL
13
LA
= 2 cycles
Bank
RDA
UA
14
"a"
Rev 1.2
Qb0Qb1
Qb0Qb1
LAL
15
LA

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