HI-8584PQI Holt Integrated Circuits, HI-8584PQI Datasheet
HI-8584PQI
Specifications of HI-8584PQI
Related parts for HI-8584PQI
HI-8584PQI Summary of contents
Page 1
... BD14 - 10 BD13 - 11 BD12 - 12 BD11 - Pin Plastic Quad Flat Pack (PQFP) (See page 13 for additional pin configuration) HOLT INTEGRATED CIRCUITS www.holtic.com HI-8584 Enhanced ARINC 429 (Top View N CWSTR 37 - ENTX 36 - N/C HI-8584PQI 35 - 429DO 34 - 429DO & N/C HI-8584PQT 32 - FFT 31 - HFT PL2 28 - PL1 27 - BD00 ...
Page 2
... Latch enable for byte 1 entered from data bus to transmitter FIFO. Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high after transmission and FIFO empty. Transmitter FIFO Half Full Transmitter FIFO Full “ ...
Page 3
... FUNCTIONAL DESCRIPTION CONTROL WORD REGISTER The HI-8584 contains a 16-bit control register which is used to con- figure the device. The control register bits CR0 - CR15 are loaded from BD00 - BD15 when CWSTR is pulsed low. The control regis- ter contents are output on the databus when SEL = 1 and pulsed low ...
Page 4
... Additionally, for data bits, the One or Zero in the upper bits of the sampling shift registers must be followed by a Null in the lower bits within the data bit time. For a Null in the word gap, three consecutive Nulls must be found in both the upper and lower bits of the sampling shift register. In this manner the minimum pulse width is guaranteed ...
Page 5
... CR2-CR11, the received ARINC 32-bit word is then checked for correct decoding and label matching before being loaded into the receive FIFO. ARINC words which do not meet the necessary 9th and 10th ARINC bit or label matching are ignored and are not loaded into the receive FIFO. The following table describes this operation ...
Page 6
... PL2 the 31 bit word (or 32 bit word if CR4=0) in the next available position of the FIFO. If TX/R, the transmitter ready flag is high (FIFO empty), then words, each bits long, may be loaded. If TX/R is low, then only the available positions may be loaded. If all 32 positions are full, the FIFO ignores further attempts to load data ...
Page 7
... In normal operation, either byte of a received data word may be read from the receiver latches first by use of SEL input. During repeater operation however, the lower byte of the data word must be read first. This is necessary because, as the data is being read also being loaded into transmitter FIFO which is always loaded LOW SPEED with the lower byte of the data word first ...
Page 8
... ARINC DATA BIT 31 BIT 32 D D/R DON'T CARE SEL EN DATA BUS t DATA BUS PL1 PL2 TX/R, HFT FFT , DATA BUS CWSTR HI-8584 DATA RATE - EXAMPLE PATTERN DATA DATA NULL NULL BIT 32 BIT 31 RECEIVER OPERATION t t SELEN t SELEN ENSEL t t ENEN D/REN t DATAEN ...
Page 9
... PL1 PL2 / CWSTR CWSTR EN1 EN2 / t CWHLD t CWSET DATA BUS Set CR1=1 Label #1 t ENDATA HI-8584 STATUS REGISTER READ CYCLE DON'T CARE t SELEN DATA VALID t ENDATA CONTROL REGISTER READ CYCLE DON'T CARE t SELEN DATA VALID t ENDATA LABEL MEMORY LOAD SEQUENCE Label #2 t ...
Page 10
... ENDAT 429DO 429DO BIT 32 RIN D D/R D/REN EN t SELEN SEL DON'T CARE t ENPL PL1 PL2 TXR ENTX 429DO 429DO HI-8584 TRANSMITTING DATA ARINC BIT ARINC BIT DATA DATA BIT 1 BIT 2 One Null Zero Null REPEATER OPERATION TIMING t END ENEN EN t ENSEL ...
Page 11
... Input Sink I IH Input Source I IL Differential C (RIN1A to RIN1B, RIN2A to RIN2B GND Input Voltage Input Voltage Input Sink I IH Input Source I IL Input Voltage Input Voltage Input Sink I IH Input Source I IL NFD Pin Output Sink OUT Output Source OUT Output Sink ...
Page 12
... Spacing - Delay - 32nd ARINC Bit to TX/R HIGH Spacing - TX/R HIGH to ENTX LOW Delay - ENTX HIGH to TXAOUT or TXBOUT: High Speed Delay - ENTX HIGH to TXAOUT or TXBOUT: Low Speed REPEATER OPERATION TIMING Delay - TX/R LOW to ENTX HIGH MASTER RESET PULSE WIDTH ARINC DATA RATE AND BIT TIMING ...
Page 13
... ADDITIONAL HI-8584 PIN CONFIGURATION ORDERING INFORMATION HI - 8584 HI-8584 FF1 - 8 HF1 - 9 D/ FF2 - 11 HF2 - 12 HI-8584CJI SEL - 13 & EN1 - 14 HI-8584CJT EN2 -15 BD15 - 16 BD14 - 17 BD13 - 18 BD12 - 19 BD11 - Pin Cerquad J-lead (See page 1 for additional pin configuration) INPUT SERIES RESISTANCE PART NUMBER BUILT-IN REQUIRED EXTERNALLY ...
Page 14
... PLASTIC QUAD FLAT PACK (PQFP) .520 BSC SQ (13.2) .063 (1.6) See Detail A .084 .013 ± (2.13 ± .32) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) HI-8584 PACKAGE DIMENSIONS max .788 (20.0) SQ. .750 .007 (19.05 .18) .190 max (4 ...