AD6653-150EBZ Analog Devices Inc, AD6653-150EBZ Datasheet - Page 28

• Manufacturer Part Number: AD6653-150EBZ
• Manufacturer: Analog Devices Inc

Specifications of AD6653-150EBZ

• Lead Free Status / Rohs Status: Compliant

AD6653
If a low jitter clock source is not available, another option is to
ac-couple a differential PECL signal to the sample clock input
pins as shown in Figure 59. The
AD9513/AD9514/AD9515/AD9516
jitter performance.
A third option is to ac-couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 60. The
AD9511/AD9512/AD9513/AD9514/AD9515/AD9516
drivers offer excellent jitter performance.
In some applications, it may be acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
the CLK+ pin should be driven directly from a CMOS gate, and the
CLK− pin should be bypassed to ground with a 0.1 μF capacitor
in parallel with a 39 kΩ resistor (see Figure 61). CLK+ can be
driven directly from a CMOS gate. Although the CLK+ input
circuit supply is AVDD (1.8 V), this input is designed to withstand
input voltages of up to 3.6 V, making the selection of the drive logic
voltage very flexible.
CLOCK
CLOCK
CLOCK
CLOCK
CLOCK
CLOCK
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
Figure 61. Single-Ended 1.8 V CMOS Sample Clock (Up to 150 MSPS)
Figure 62. Single-Ended 3.3 V CMOS Sample Clock (Up to 150 MSPS)
50kΩ
50kΩ
Figure 60. Differential LVDS Sample Clock (Up to 625 MHz)
Figure 59. Differential PECL Sample Clock (Up to 625 MHz)
50Ω
50Ω
0.1µF
0.1µF
0.1µF
0.1µF
50kΩ
0.1µF
0.1µF
50kΩ
V
V
CC
CC
1kΩ
1kΩ
1kΩ
1kΩ
PECL DRIVER
LVDS DRIVER
CMOS DRIVER
AD951x
AD951x
CMOS DRIVER
AD951x
AD951x
240Ω
AD9510/AD9511/AD9512/
0.1µF
clock drivers offer excellent
OPTIONAL
OPTIONAL
240Ω
100Ω
100Ω
100Ω
100Ω
39kΩ
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
CLK+
CLK–
CLK+
CLK–
CLK+
CLK–
CLK+
CLK–
AD6653
AD9510/
AD6653
AD6653
AD6653
ADC
ADC
ADC
ADC
clock
Rev. 0 | Page 28 of 80
Input Clock Divider
The AD6653 contains an input clock divider with the ability to
divide the input clock by integer values between 1 and 8. If a
divide ratio other than 1 is selected, the duty cycle stabilizer is
automatically enabled.
The AD6653 clock divider can be synchronized using the external
SYNC input. Bit 1 and Bit 2 of Register 0x100 allow the clock
divider to be resynchronized on every SYNC signal or only on
the first SYNC signal after the register is written. A valid SYNC
causes the clock divider to reset to its initial state.
This synchronization feature allows multiple parts to have their
clock dividers aligned to guarantee simultaneous input sampling.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. Commonly, a ±5% tolerance is
required on the clock duty cycle to maintain dynamic performance
characteristics.
The AD6653 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows the user to
provide a wide range of clock input duty cycles without affecting
performance of the AD6653. Noise and distortion performance
are nearly flat for a wide range of duty cycles with the DCS on,
as shown in Figure 44.
Jitter on the rising edge of the input clock is still of paramount
concern and is not easily reduced by the internal stabilization
circuit. The duty cycle control loop does not function for clock
rates less than 20 MHz nominally. The loop has a time constant
associated with it that must be considered when the clock rate
can change dynamically. A wait time of 1.5 μs to 5 μs is required
after a dynamic clock frequency increase or decrease before the
DCS loop is relocked to the input signal. During the time period
that the loop is not locked, the DCS loop is bypassed, and internal
device timing is dependent on the duty cycle of the input clock
signal. In such applications, it may be appropriate to disable the
duty cycle stabilizer. In all other applications, enabling the DCS
circuit is recommended to maximize ac performance.
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR at a given input
frequency (f
In the equation, the rms aperture jitter represents the root mean
square of all jitter sources, which include the clock input, the
analog input signal, and the ADC aperture jitter specification.
IF undersampling applications are particularly sensitive to jitter,
as shown in Figure 63.
SNR
=
−
IN
20
) due to jitter (t
log
[
2
πf
IN
×
t
J
]
J
) can be calculated by