IS42S16100F-7BLI ISSI, Integrated Silicon Solution Inc, IS42S16100F-7BLI Datasheet - Page 36

• Manufacturer Part Number: IS42S16100F-7BLI
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS42S16100F-7BLI

• Lead Free Status / Rohs Status: Compliant

IS42/45S16100F, IS42VS16100F
Precharge
The precharge command sets the bank selected by
pin A11 to the precharged state. This command can be
executed at a time t
command to the same bank. The selected bank goes to
the idle state at a time t
precharge command, and an active command can be
executed again for that bank.
If pin A10 is low when this command is executed, the bank
selected by pin A11 will be precharged, and if pin A10 is
HIGH, both banks will be precharged at the same time.
This input to pin A11 is ignored in the latter case.
36
CAS latency = 3, burstlength = 4
CAS latency = 2, burstlength = 4
COMMAND
COMMAND
CLK
CLK
DQ
DQ
ras
following the execution of an active
rp
READ (CA=A, BANK 0)
READ (CA=A, BANK 0)
following the execution of the
READ A0
READ A0
PRECHARGE (BANK 0)
D
OUT
A0 D
D
PRE 0
PRE 0
OUT
OUT
Read Cycle Interruption
Using the Precharge Command
A read cycle can be interrupted by the execution of the
precharge command before that cycle completes. The
delay time (t
command to the completion of the burst output is the
clock cycle of CAS latency.
A0 D
A1 D
PRECHARGE (BANK 0)
Integrated Silicon Solution, Inc. — www.issi.com
CAS Latency
t
RQL
OUT
OUT
t
rql
rql
A1 D
A2
t
RQL
) from the execution of the precharge
OUT
HI-Z
A2
HI-Z
3
3
2
2
06/03/2010
Rev. 00C