HI-8282APQI Holt Integrated Circuits, HI-8282APQI Datasheet
HI-8282APQI
Specifications of HI-8282APQI
Related parts for HI-8282APQI
HI-8282APQI Summary of contents
Page 1
... BD15 - 7 BD14 - 8 BD13 - 9 BD12 - 10 BD11 - 11 44-Pin Plastic Quad Flat Pack (PQFP) HOLT INTEGRATED CIRCUITS www.holtic.com HI-8282A ARINC 429 (Top View N N HI-8282APQI 30 - ENTX 29 - HI-8282APQT 28 - 429DO 27 - TX/R HI-8282APQM BD00 23 - BD01 (See page 10 for additional Package Pin Configurations) CWSTRX 429DO PL2 PL1 ...
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... Latch enable for byte 1 entered from data bus to transmitter FIFO. Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high after transmission and FIFO empty. "ONES" data output from transmitter. ...
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... This option is especially useful in applications where lightning protection circuitry is also required. Each side of the ARINC bus must be connected through a 10K to 15K ohm series resistor in order for the chip to detect the correct ARINC COMPARATORS levels. The typical 10 volt differential signal is translated and input to a window comparator and latch ...
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... When the receive sig- nal is outside the differential voltage range defined for any shift register, a low bit is clocked. Only one shift register can clock a high bit for any given sample. All three registers clock low bits if the differential input voltage is between de- fined state voltage bands ...
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... DATA BUS HI-8282A BD12 control word bit is set low, the 32nd bit transmitted will make parity odd. If the control bit is high, the parity is even. SELF TEST If the BD05 control word bit is set low, 429DO or internally connected to the receivers inputs, bypassing the interface circuitry ...
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... SEL input. During repeater operation however, data word lower byte must always be PL1 at the same time as read first. While the data is being read loading concurrently SEL is into the Transmit FIFO, which always loads lower byte first. DATA RATE - EXAMPLE PATTERN ...
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... ENTX t ENDAT 429DO or 429DO 429DI BIT 32 D D/R D/REN EN t SELEN SEL DON'T CARE t ENPL PL1 PL2 TX/R ENTX 429DO HI-8282A TRANSMITTER OPERATION BYTE 1 VALID t DWSET t DWHLD PL12 TRANSMITTING DATA ARINC BIT DATA DATA BIT 1 BIT 2 REPEATER OPERATION TIMING t END ENEN ...
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... Input Source I IL Differential C Pins GND Vcc C H Input Voltage Input Voltage Input Sink I IH Input Source ENTX, CWSTR , CLK & MR Input Voltage Input Voltage Input Sink I IH Input Source I IL 429DO & TX CLK Output Sink Output Source OUT Output Sink I V ...
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... Setup - DATA BUS Valid to Hold - Delay - TRANSMISSION TIMING Spacing - Delay - ENTX HIGH to TXA(OUT) or TXB(OUT): High Speed Delay - ENTX HIGH to TXA(OUT) or TXB(OUT): Low Speed Delay - 32nd ARINC Bit to TX/R HIGH Spacing - TX/R HIGH to ENTX L0W REPEATER OPERATION TIMING Delay - TX/R LOW to ENTX HIGH ...
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... REC.2 DATA FLAG D/R2 ) (REC. BYTE SELECT) SEL ( REC. 1 OUTPUT ENABLE ) EN1 ( REC. 2 OUTPUT ENABLE ) EN2 BD15 BD14 BD13 BD12 BD11 BD10 BD09 BD08 BD07 BD06 HI-8282ACDI / CDT / CDM HOLT INTEGRATED CIRCUITS MASTER RESET ) CLK (XMIT CLOCK OUT CLK (MASTER CLK IN ...
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... TO +125° -55°C TO +125°C M PACKAGE DESCRIPTION CD 40 PIN CERAMIC SIDE BRAZED DIP (40C) 44 PIN J-LEAD CERQUAD (44U PIN CERAMIC LEADLESS CHIP CARRIER (44S) CL INPUT SERIES RESISTANCE BUILT-IN REQUIRED EXTERNALLY 35 Kohm -10 25 Kohm 10K to 15K ohm (Note 1) LEAD FINISH ...
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... REVISION HISTORY Revision Date Description of Change DS8282A, Rev. G 02/01/09 Clarified the “T” temperature range. Clarified series resistance values for “-10” devices. HI-8282A HOLT INTEGRATED CIRCUITS 12 ...
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... Standard 95) 44-PIN J-LEAD CERQUAD .650 ±.010 (16.510 ±.254) SQ. .039 ±.005 (.990 ±.127) .019 ±.002 (.483 ± .051) HI-8282A PACKAGE DIMENSIONS 2.020 max (51.308) .595 ±.010 (15.113 ±.254) .050 typ (1.270) .085 ±.009 (2.159 ± ...
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... SQ. See Detail A .063 MAX. (1.6) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) HI-8282A PACKAGE DIMENSIONS PIN NO. 1 IDENT .045 x 45° .653 ±.004 (16.586 ±.102) SQ. See Detail A .610 ±.020 (15.494±.508) .394 ± ...
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... CERAMIC LEADLESS CHIP CARRIER .020 INDEX PIN 1 (.508) .651 ±.011 (16.535 ±.279) SQ. BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) HI-8282A PACKAGE DIMENSIONS .040 x 45° 3 PLCS (1.016 x 45°) .075 ±.004 (1.905 ± ...