MT45W2MW16PGA-70 WT Micron Technology Inc, MT45W2MW16PGA-70 WT Datasheet - Page 13

• Manufacturer Part Number: MT45W2MW16PGA-70 WT
• Manufacturer: Micron Technology Inc

Specifications of MT45W2MW16PGA-70 WT

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Figure 8:
Deep Power-Down Operation
PDF: 09005aef82832fa7 / Source: 09005aef82832f97
32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 12/09 EN
Software Access PAR Functionality
Deep power-down (DPD) operation disables all refresh-related activity. This mode is
used when the system does not require the storage provided by the CellularRAM device.
Any stored data will become corrupted when DPD is entered. When refresh activity has
been re-enabled, the CellularRAM device will require 150µs to perform an initialization
procedure before normal operations can resume. READ and WRITE operations are
ignored during DPD operation.
The device can only enter DPD if the SLEEP bit in the CR has been set LOW (CR[4] = 0).
DPD is initiated by bringing ZZ# to the LOW state for longer than 10µs. Returning ZZ# to
HIGH will cause the device to exit DPD and begin a 150µs initialization process. During
this 150µs period, the current consumption will be higher than the specified standby
levels but considerably lower than the active current specification.
Driving ZZ# LOW will place the device in the PAR mode if the SLEEP bit in the CR has
been set HIGH (CR[4] = 1).
The device should not be put into DPD using CR software access.
NO
PAR permanently
independent of
To enable PAR,
bring ZZ# LOW
Change to ZZ#
functionality;
Powe r-Up
executed?
ZZ# level.
enabled
for 10µs.
Software
LOAD
32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory
YES
13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Low-Power Operation
©2007 Micron Technology, Inc. All rights reserved.