MT45W2MW16PGA-70 WT Micron Technology Inc, MT45W2MW16PGA-70 WT Datasheet - Page 12

• Manufacturer Part Number: MT45W2MW16PGA-70 WT
• Manufacturer: Micron Technology Inc

Specifications of MT45W2MW16PGA-70 WT

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Low-Power Operation
Standby Mode Operation
Temperature-Compensated Refresh
Partial-Array Refresh
PDF: 09005aef82832fa7 / Source: 09005aef82832f97
32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 12/09 EN
During standby, the device current consumption is reduced to the level necessary to
perform the DRAM REFRESH operation on the full array. Standby operation occurs
when CE# and ZZ# are HIGH.
The device will enter a reduced power state upon completion of READ and WRITE oper-
ations where the address and control inputs remain static for an extended period of
time. This mode will continue until a change occurs to the address or control inputs.
Temperature-compensated refresh (TCR) allows for adequate refresh at different
temperatures. This CellularRAM device includes an on-chip temperature sensor. It
continually adjusts the refresh rate according to the operating temperature.
Partial-array refresh (PAR) restricts REFRESH operation to a portion of the total memory
array. This feature enables the system to reduce refresh current by only refreshing that
part of the memory array that is absolutely necessary. The refresh options are full array,
one-half array, one-quarter array, one-eighth array, or none of the array. Data stored in
addresses not receiving refresh will become corrupted. The mapping of these partitions
can start at either the beginning or the end of the address map (Table 3 on page 17).
READ and WRITE operations are ignored during PAR operation.
The device only enters PAR mode if the SLEEP bit in the CR has been set HIGH
(CR[4] = 1). PAR can be initiated by bring the ZZ# ball to the LOW state for longer than
10µs. Returning ZZ# to HIGH will cause an exit from PAR and the entire array will be
immediately available for READ and WRITE operations.
Alternatively, PAR can be initiated using the CR software access sequence (see “Software
Access to the Configuration Register” on page 14). PAR is enabled immediately upon
setting CR[4] to “1” using this method. However, using software access to write to the CR
alters the function of ZZ# so that ZZ# LOW no longer initiates PAR, although ZZ#
continues to enable WRITEs to the CR. This functional change persists until the next
time the device is powered up (see Figure 8 on page 13).
32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
Low-Power Operation
©2007 Micron Technology, Inc. All rights reserved.