MT48H16M16LFBF-75 IT:G Micron Technology Inc, MT48H16M16LFBF-75 IT:G Datasheet - Page 82
![](/photos/31/34/313423/557-54-vfbga_sml.jpg)
MT48H16M16LFBF-75 IT:G
Manufacturer Part Number
MT48H16M16LFBF-75 IT:G
Description
Manufacturer
Micron Technology Inc
Type
Mobile SDRAMr
Datasheet
1.MT48H16M16LFBF-75_ITG.pdf
(86 pages)
Specifications of MT48H16M16LFBF-75 IT:G
Organization
16Mx16
Density
256Mb
Address Bus
15b
Access Time (max)
8/6ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
1.8V
Package Type
VFBGA
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
1.95V
Operating Supply Voltage (min)
1.7V
Supply Current
80mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Compliant
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Clock Suspend
Figure 50: Clock Suspend During WRITE Burst
PDF: 09005aef834c13d2
256mb_mobile_sdram_y36n.pdf - Rev. I 11/09 EN
Note:
Command
Internal
Address
The clock suspend mode occurs when a column access/burst is in progress and CKE is
registered LOW. In the clock suspend mode, the internal clock is deactivated, freezing
the synchronous logic.
For each positive clock edge on which CKE is sampled LOW, the next internal positive
clock edge is suspended. Any command or data present on the input balls when an in-
ternal clock edge is suspended will be ignored; any data present on the DQ balls
remains driven; and burst counters are not incremented, as long as the clock is suspended.
Exit clock suspend mode by registering CKE HIGH; the internal clock and related opera-
tion will resume on the subsequent positive clock edge.
clock
1. For this example, BL = 4 or greater, and DQM is LOW.
CKE
CLK
D
IN
NOP
T0
WRITE
Bank,
Col n
D
T1
IN
256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
T2
82
T3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
NOP
D
T4
IN
Don’t Care
T5
NOP
D
IN
©2008 Micron Technology, Inc. All rights reserved.
Clock Suspend
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