MT46V16M16TG-5BLIT Micron Technology Inc, MT46V16M16TG-5BLIT Datasheet - Page 86

• Manufacturer Part Number: MT46V16M16TG-5BLIT
• Manufacturer: Micron Technology Inc

Specifications of MT46V16M16TG-5BLIT

• Lead Free Status / Rohs Status: Not Compliant

Figure 49:
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
Command
BA0, BA1
Address
DQ
DQS
CK#
CKE
A10
DM
CK
5
t IS
t IS
NOP
T0
WRITE – DM Operation
t IH
1
t IH
Notes:
Bank x
t IS
t IS
ACT
Row
Row
T1
1. NOP commands are shown for ease of illustration; other commands may be valid at these
2. BL = 4.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T8.
5. DI b = data-in from column b; subsequent elements are provided in the programmed order.
6. See Figure 50 on page 85 for detailed DQ timing.
t IH
t IH
t CK
times.
t RCD
t RAS
NOP
T2
1
t CH
t CL
Bank x
WRITE
t IS
3
Col n
T3
t DQSS (NOM)
t IH
2
t WPRES t WPRE
t DS
84
NOP
T4
DI
b
1
t DH
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T4n
t DQSL
NOP
T5
t DQSH
256Mb: x4, x8, x16 DDR SDRAM
1
T5n
t WPST
NOP
T6
1
Transitioning Data
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t WR
NOP
T7
1
Operations
All banks
One bank
Bank x
Don’t Care
PRE
T8
4
t RP