ADV7330KST Analog Devices Inc, ADV7330KST Datasheet - Page 32

• Manufacturer Part Number: ADV7330KST
• Manufacturer: Analog Devices Inc

Specifications of ADV7330KST

• Operating Supply Voltage (typ): 2.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: LQFP
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Compliant

ADV7330
Reset Sequence
A reset is activated with a high-to-low transition on the RESET pin
(Pin 33) according to the Timing Specifications. The ADV7330
will revert to the default output configuration.
Figure 24 illustrates the RESET sequence timing.
SD VCR FF/RW Sync
[Subaddress 42h, Bit 5]
In DVD record applications where the encoder is used with a
decoder, the VCR FF/RW sync control bit can be used for
nonstandard input video, i.e., in fast forward or rewind modes.
In fast forward mode, the sync information at the start of a new
field in the incoming video usually occurs before the correct
DIGITAL TIMING
PIXEL DATA
RTC
NOTES
1
2
3
RESET
F
BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY
REGISTERS OF THE ADV7330.
SEQUENCE BIT.
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED.
NTSC: 0 = NO CHANGE.
RESET BIT. RESET ADV7330 DSS.
A, B, C
VALID
DACs
SC
e.g., VCR OR CABLE
COMPOSITE VIDEO
PLL INCREMENT IS 22 BITS LONG, VALUE LOADED INTO ADV7330, F
XXXXXX
XXXXXX
H/L TRANSITION
COUNT START
TIME SLOT: 01
128
LOW
ADV7183A
DECODER
13
VIDEO
LCC1
SUBCARRIER
14 BITS
PHASE
Figure 23. RTC Timing and Connections
Figure 24. RESET Timing Sequence
P17–P10
GLL
14
0
RESERVED
DIGITAL TIMING SIGNALS SUPPRESSED
4 BITS
21
19
–32–
CLKIN
RTC_SCR_TR
OFF
Y7–Y0
number of lines/fields are reached. In rewind mode, this sync
signal usually occurs after the total number of lines/fields are
reached. Conventionally this means that the output video will
have corrupted field signals, one generated by the incoming video
and one generated when the internal lines/field counters reach
the end of a field.
When the VCR FF/RW sync control is enabled [Subaddress 42h,
Bit 5], the lines/field counters are updated according to the
incoming vsync signal, and the analog output matches the incoming
vsync signal.
This control is available in all slave timing modes except
Slave Mode 0.
SAMPLE
F
ADV7330
VALID
SC
SC
DSS REGISTER IS F
PLL INCREMENT
SAMPLE
INVALID
DAC A
DAC B
DAC C
1
SC
PLL INCREMENTS BITS 21:0 PLUS
LOCKED
CLOCK
8/LINE
SEQUENCE
BIT
0
2
RESERVED
6768
5 BITS
RESET
RESERVED
BIT
TIMING ACTIVE
VALID VIDEO
3
REV. B