ADV7330KST Analog Devices Inc, ADV7330KST Datasheet - Page 27

• Manufacturer Part Number: ADV7330KST
• Manufacturer: Analog Devices Inc

Specifications of ADV7330KST

• Operating Supply Voltage (typ): 2.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: LQFP
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Compliant

INPUT CONFIGURATION
Note that the ADV7330 defaults to progressive scan 54 MHz
mode on power-up. Address(01h): Input Mode = 011
Standard Definition
Address(01h): Input Mode = 000
The 8-bit multiplexed input data is input on Pins Y7–Y0, with Y0
being the LSB. Input standards supported are ITU-R BT.601/656.
In 16-bit input mode the Y pixel data is input on Pins Y7–Y0
and CrCb data on Pins C7–C0.
Input sync signals are optional and are input on the VSYNC_I/P,
HSYNC_I/P, and BLANK_I/P pins.
Progressive Scan or HDTV Mode
Address(01h): Input Mode 001 or 010, Respectively
YCrCb progressive scan, HDTV, or any other HD YCrCb data
can be input in 4:2:2. In 4:2:2 input mode, the Y data is input
on Pins Y7–Y0 and the CrCb data on Pins C7–C0.
If the YCrCb data does not conform to SMPTE 293M (525p),
ITU-R BT.1358M (625p), SMPTE 274M (1080i), SMPTE
296M (720p), or BTA T-1004/1362, the async timing mode
must be used.
REV. B
Figure 17. Progressive Scan Input Mode
DECODER
PROGRESSIVE
INTERLACED
MPEG2
DECODER
YCrCb
MPEG2
Figure 16. SD Input Mode
TO
YCrCb
27MHz
CbCr
Y
27MHz
3
8
8
8
3
VSYNC_I/P
HSYNC_I/P
BLANK_I/P
CLKIN
Y[7:0]
ADV7330
CLKIN
C[7:0]
Y[7:0]
VSYNC_I/P
HSYNC_I/P
BLANK_I/P
ADV7330
–27–
Progressive Scan at 27 MHz (Dual Edge) or 54 MHz
Address(01h): Input Mode 100 or 111, Respectively
YCrCb progressive scan data can be input at 27 MHz or 54 MHz.
The input data is interleaved onto a single 8-bit bus and is input
on Pins Y7–Y0. When a 27 MHz clock is supplied, the data is
clocked in on the rising and falling edge of the input clock and
CLOCK EDGE [Address 01h, Bit 1] must be set accordingly.
The following figures show the possible conditions.
With a 54 MHz clock, the data is latched on every rising edge.
PIXEL INPUT
CLKIN
CLKIN
Y7–Y0
Y7–Y0
Figure 18a. Cb Data on Rising Edge—Clock Edge
Address 01h Bit 1 Should be Set to 0
Figure 18b. Y Data on Rising Edge—Clock Edge
Address 01h Bit 1 Should be Set to 1
CLKIN
Figure 18c. Input Sequence in PS Bit Interleaved
Mode (EAV/SAV)
DATA
Figure 19. 1
3FF
3FF
PROGRESSIVE
DECODER
INTERLACED
MPEG2
YCrCb
3FF
TO
00
00
00
27MHz OR 54MHz
8-Bit PS at 27 MHz or 54 MHz
00
00
YCrCb
00
8
3
XY
XY
XY
Cb0
Y0
Cb0
CLKIN
Y[7:0]
VSYNC_I/P
HSYNC_I/P
BLANK_I/P
ADV7330
Cb0
Y0
ADV7330
Y0
Cr0
Y1
Cr0
Cr0
Y1
Y1