IS42S16100E-5T-TR ISSI, Integrated Silicon Solution Inc, IS42S16100E-5T-TR Datasheet - Page 26

• Manufacturer Part Number: IS42S16100E-5T-TR
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS42S16100E-5T-TR

• Organization: 1Mx16
• Density: 16Mb
• Address Bus: 12b
• Access Time (max): 6/5ns
• Maximum Clock Rate: 200MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 170mA
• Pin Count: 50
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

IS42S16100E, IC42S16100E
Read With Auto-Precharge
The read with auto-precharge command first executes a
burst read operation and then puts the selected bank in
the precharged state automatically. After the precharge
completes, the bank goes to the idle state. Thus this
command performs a read command and a precharge
command in a single operation.
During this operation, the delay period (t
last burst data output and the start of the precharge opera-
tion differs depending on the CAS latency setting.
When the CAS latency setting is two, the precharge opera-
tion starts on one clock cycle before the last burst data is
output (t
26
CAS latency = 3, burstlength = 4
CAS latency = 2, burstlength = 4
COMMAND
COMMAND
pql
READ WITH AUTO-PRECHARGE
READ WITH AUTO-PRECHARGE
CLK
CLK
= –1). When the CAS latency setting is
DQ
DQ
(BANK 0)
(BANK 0)
READA 0
READA 0
pql
D
) between the
OUT
PRECHARGE START
PRECHARGE START
0
D
D
OUT
OUT
0
1
three, the precharge operation starts on two clock cycles
before the last burst data is output (t
the selected bank can be made active after a delay of t
from the start position of this precharge operation.
The selected bank must be set to the active state before
executing this command.
The auto-precharge function is invalid if the burst length
is set to full page.
D
D
OUT
OUT
Integrated Silicon Solution, Inc. — www.issi.com
CAS Latency
t
PQL
1
2
t
pql
t
D
D
RP
OUT
OUT
t
PQL
2
3
t
RP
D
ACT 0
OUT
3
–2
3
pql
= –2). Therefore,
ACT 0
–1
2
01/22/08
Rev. C
rp