TX14D12VM1CAA HITACHI, TX14D12VM1CAA Datasheet - Page 14

• Manufacturer Part Number: TX14D12VM1CAA
• Manufacturer: HITACHI

Specifications of TX14D12VM1CAA

• Lead Free Status / Rohs Status: Compliant

KAOHSIUNG HITACHI
ELECTRONICS CO.,LTD.
8.INTERFACE TIMING
Note 1 : DTMG is definition of the above timing for Hsync and Vsync.
Note 2 : No matter when Hsync and Vsync is inputted ,this LCM can be drove
Hsync
Vsync
8.1 Timing Chart
DCLK
DATA
DTMG
Hsync
DTMG
DTMG
DCLK
Vsync
(Data is latched negative edge trigger of DCLK)
only DTMG Signal. DTMG should be set to low level when it is not input
valid data.
Invalid Data
t
t
WH
WV
t
CLKL
t
t
CLK
VBP
t
SV
1.5V
t
HH
DATE Nov.12,’10
t
t
t
HI
HD
HBP
t
VSYNC，HSYNC，DTMG，
R0～5，G0～5，B0～5
SH
t
t
SD
SI
t
t
VP
WCH
t
t
HP
Sh.
No.
HV
t
WCL
t
t
Hr
Ir
7B64PS 2708-TX14D12VM1CAA-5
,t
,t
Vr
Dr
V
IL
V
IH
ma x.
mi n.
t
fCLK
t
t
Hf
If
,t
,t
Vf
Df
t
t
HFP
VFP
t
rCLK
Invalid Data
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