AD9779ABSVZ Analog Devices Inc, AD9779ABSVZ Datasheet - Page 36

• Manufacturer Part Number: AD9779ABSVZ
• Description: IC DAC 16BIT 1.0GSPS 100TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9779ABSVZ

• Data Interface: Serial
• Design Resources: Interfacing ADL5370 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0016) Interfacing ADL5371 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0017) Interfacing ADL5372 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0018) Interfacing ADL5373 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0019) Interfacing ADL5374 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0020) Interfacing ADL5375 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0021)
• Number Of Bits: 16
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 300mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Resolution (bits): 16bit
• Sampling Rate: 1GSPS
• Input Channel Type: Parallel
• Digital Ic Case Style: QFP
• No. Of Pins: 100
• Operating Temperature Range: -40°C To +85°C
• Number Of Channels: 2
• Resolution: 16b
• Interface Type: Parallel
• Single Supply Voltage (typ): 3.3V
• Dual Supply Voltage (typ): Not RequiredV
• Architecture: Interpolation Filter
• Power Supply Requirement: Analog and Digital
• Output Type: Current
• Single Supply Voltage (min): 3.13V
• Single Supply Voltage (max): 3.47V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TQFP EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9779A-EBZ - BOARD EVALUATION FOR AD9779A
• Settling Time: -
• Lead Free Status / Rohs Status: Compliant

AD9776A/AD9778A/AD9779A
SOURCING THE DAC SAMPLE CLOCK
The AD9776A/AD9778A/AD9779A offer two modes of sourcing
the DAC sample clock (DACCLK). The first mode employs an
on-chip clock multiplier that accepts a reference clock operating
at the lower input frequency, most commonly the data input
frequency. The on-chip PLL then multiplies the reference clock
up to a higher frequency, which can then be used to generate all
of the internal clocks required by the DAC. The clock multiplier
provides a high quality clock that meets the performance require-
ments of most applications. Using the on-chip clock multiplier
removes the burden of generating and distributing the high
speed DACCLK at the board level. The second mode bypasses
the clock multiplier circuitry and allows DACCLK to be directly
sourced through the REFCLK pins. This mode enables the user
to source a very high quality input clock directly to the DAC
core. Sourcing the DACCLK directly through the REFCLK pins
may be necessary in demanding applications that require the
lowest possible DAC output noise at higher output frequencies.
In either case (using the on-chip clock multiplier, or sourcing
the DACCLK directly though the REFCLK pins), it is necessary
that the REFCLK signal have low jitter to maximize the DAC
noise performance.
DIRECT CLOCKING
When the PLL is disabled (Register 0x09, Bit 7 = 0), the REFCLK
input is used directly as the DAC sample clock (DACCLK). The
frequency of REFCLK needs to be the input data rate multiplied
by the interpolation factor (and by an additional factor of two if
zero stuffing is enabled).
CLOCK MULTIPLICATION
When the PLL is enabled (Register 0x09, Bit 7 = 1), the clock
multiplication circuit generates the DAC sample clock from the
lower rate REFCLK input. The functional diagram of the clock
multiplier is shown in Figure 71.
(PIN 5, PIN 6)
The clock multiplier circuit operates such that the VCO outputs
a frequency, f
multiplied by N1 × N2.
REFCLK
VCO
PLL ENABLE
PIN 65 AND
DETECTOR
PLL LOCK
0x0A <1>
DETECT
, equal to the REFCLK input signal frequency
PHASE
0x09 <7>
Figure 71. Clock Multiplier Circuit
0x09 <4:3>
PLL LOOP
DIVISOR
÷N
2
FILTER
LOOP
DACCLK
0x09 <6:5>
PLL VCO
DIVISOR
÷N
INTERPOLATION
1
0x01 <7:6>
FACTOR
÷IF
VCO
ADC
DATACLK OUT (PIN 37)
0x0A <7:5>
PLL CONTROL
VOLTAGE
0x08 <7:2>
VCO BAND
SELECT
Rev. A | Page 36 of 60
The DAC sample clock frequency, f
The values of N1 and N2 must be chosen to keep f
optimal operating range of 1.0 GHz to 2.0 GHz. Once, the
VCO output frequency is known, the correct VCO band select
(Register 0x08, Bits<7:2>) value can be chosen.
PLL Bias Settings
There are three bias settings for the PLL circuitry that should be
programmed to their nominal values. The PLL values shown in
Table 20 are the recommended settings for these parameters.
Table 20. PLL Settings
PLL SPI Control
PLL Loop Bandwidth
PLL VCO Drive
PLL Bias
The PLL loop bandwidth variable configures the bandwidth of
the PLL loop filter. A setting of 00000 configures the bandwidth
to be approximately 1 MHz. A setting of 11111 configures the
bandwidth to be approximately 10 MHz. The optimal value of
01111 sets the loop bandwidth to be approximately 3 MHz.
Configuring the PLL Band Select Value
The PLL VCO has a valid operating range from approximately
1.0 GHz to 2.0 GHz. This range is covered in 63 overlapping
frequency bands, as shown in Table 21. For any desired VCO
output frequency, there are multiple valid PLL band select values.
It is important to note that the data shown in Table 21 is for a
typical device. Device-to-device variations can shift the actual
VCO output frequency range by 30 MHz to 40 MHz. In addition,
the VCO output frequency varies as a function of temperature.
Therefore, it is required that the optimal PLL band select value
be determined for each individual device at the particular
operating temperature.
The device has an automatic PLL band select feature on-chip.
When enabled, the device determines the optimal PLL band
setting for the device at the given temperature. This setting holds
for a ±60°C temperature swing in ambient temperature. If the
device is operated in an environment that experiences a larger
temperature swing, an offset should be applied to the automatically
selected PLL band. The following procedure outlines a method
for setting the PLL band select value for a device operating at a
particular temperature that holds for a change in ambient temper-
ature over the total −40°C to +85°C operating range of the device
without further user intervention. Note that REFCLK must be
applied to the device during this procedure.
f
f
VCO
DACCLK
=
f
=
REFCLK
f
REFCLK
×
(
N1
×
Register
0x0A
0x08
0x09
N2
×
Address
N2
)
DACCLK
Bits
<4:0>
<1:0>
<2:0>
, is equal to
Optimal Setting
01111
11
011
VCO
in the