AD9779BSVZ Analog Devices Inc, AD9779BSVZ Datasheet - Page 26

• Manufacturer Part Number: AD9779BSVZ
• Description: IC DAC 16BIT DUAL 1GSPS 100TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9779BSVZ

• Data Interface: Serial
• Number Of Bits: 16
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 300mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Resolution (bits): 16bit
• Sampling Rate: 1GSPS
• Input Channel Type: Parallel
• Digital Ic Case Style: QFP
• No. Of Pins: 160
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9779A-EBZ - BOARD EVALUATION FOR AD9779A
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9776/AD9778/AD9779
For multibyte transfers, this address is the starting byte address.
The remaining register addresses are generated by the device
based on the LSB-first bit (Register 0x00, Bit 6).
Table 10. Byte Transfer Count
N1
0
0
1
1
Serial Interface Port Pin Descriptions
Serial Clock (SCLK)
The serial clock pin synchronizes data to and from the device
and to run the internal state machines. The maximum frequency
of SCLK is 40 MHz. All data input is registered on the rising
edge of SCLK. All data is driven out on the falling edge of SCLK.
Chip Select (CSB)
Active low input starts and gates a communication cycle. It
allows more than one device to be used on the same serial
communications lines. The SDO and SDIO pins go to a high
impedance state when this input is high. Chip select should
stay low during the entire communication cycle.
Serial Data I/O (SDIO)
Data is always written into the device on this pin. However, this
pin can be used as a bidirectional data line. The configuration
of this pin is controlled by Register 0x00, Bit 7. The default is
Logic 0, configuring the SDIO pin as unidirectional.
Serial Data Out (SDO)
Data is read from this pin for protocols that use separate lines
for transmitting and receiving data. In the case where the device
operates in a single bidirectional I/O mode, this pin does not
output data and is set to a high impedance state.
MSB/LSB TRANSFERS
The serial port can support both MSB-first and LSB-first data
formats. This functionality is controlled by Register Bit LSB_FIRST
(Register 0x00, Bit 6). The default is MSB-first (LSB-first = 0).
When LSB-first = 0 (MSB-first) the instruction and data bit
must be written from MSB to LSB. Multibyte data transfers in
MSB-first format start with an instruction byte that includes the
register address of the most significant data byte. Subsequent data
bytes should follow from high address to low address. In MSB-first
mode, the serial port internal byte address generator decrements
for each data byte of the multibyte communication cycle.
N0
0
1
0
1
Description
Transfer one byte
Transfer three bytes
Transfer two bytes
Transfer four bytes
Rev. A | Page 26 of 56
When LSB-first = 1 (LSB-first) the instruction and data bit
must be written from LSB to MSB. Multibyte data transfers in
LSB-first format start with an instruction byte that includes the
register address of the least significant data byte followed by mul-
tiple data bytes. The serial port internal byte address generator
increments for each byte of the multibyte communication cycle.
The serial port controller data address decrements from the
data address written toward 0x00 for multibyte I/O operations if
the MSB-first mode is active. The serial port controller address
increments from the data address written toward 0x1F for
multibyte I/O operations if the LSB-first mode is active.
SCLK
SCLK
SCLK
SCLK
SDIO
SDIO
SDIO
SDIO
SDO
SDO
CSB
CSB
SDO
CSB
CSB
Figure 53. Serial Register Interface Timing MSB-First
R/W N1 N0
Figure 54. Serial Register Interface Timing LSB-First
A0
Figure 55. Timing Diagram for SPI Register Write
Figure 56. Timing Diagram for SPI Register Read
INSTRUCTION BIT 7
INSTRUCTION CYCLE
INSTRUCTION CYCLE
A1 A2
t
t
DS
DS
DATA BIT n
A4 A3
A3 A4
t
PWH
t
t
DH
DV
t
A2 A1
N0 N1 R/W D0
SCLK
t
PWL
INSTRUCTION BIT 6
A0 D7 D6
DATA BIT n –1
D0
D7 D6
0
0
DATA TRANSFER CYCLE
DATA TRANSFER CYCLE
D1
D1
N
N
0
0
D5
D5
D2
D2
N
N
0
0
D3
D4
D3
D4
0
N
0
N
D2
D2
D5
D5
N
0
0
N
D1
D6
D1
D6
0
N
N
0
D0
D0
D7
D7
0
0
N
N