EMC6D102-CZC-TR Standard Microsystems (SMSC), EMC6D102-CZC-TR Datasheet - Page 75

• Manufacturer Part Number: EMC6D102-CZC-TR
• Manufacturer: Standard Microsystems (SMSC)

Specifications of EMC6D102-CZC-TR

• Operating Current: 3mA
• Operating Temperature Classification: Commercial
• Package Type: SSOP
• Lead Free Status / Rohs Status: Compliant

Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features
Datasheet
SMSC EMC6D102
7.2.41
7.2.42
Register
Address
Register
Address
97h
94h
95h
96h
Read/
Write
Read/
Write
R/W
R/W
R/W
R/W
111=950msec
Note: PWM Max stretch time determines the maximum time for monitoring the tach input.
Registers 94h-96h: PWMx Option Registers
These registers become read only when the Lock bit is set. Any further attempts to write to these
registers shall have no effect.
Bits[1:0] Tachs reading registers associated with PWMx are updated: (Mode 2 only)
00=once a second (default)
01=twice a second
1x=every 300msec
Bit[2] Snap to Zero (SZEN)
This bit determines if the PWM output ramps down to OFF or if it is immediately set to zero.
0=Step Down the PWMx output to Off at the programmed Ramp Rate
1=Transition PWMx to Off immediately when the calculated duty cycle is 00h (default)
Bit[4:3] Guard time (Mode 2 only)
00=63 clocks (90kHz clocks ~ 700usec)
01=32 clocks (90kHz clocks ~ 356usec) (default)
10=16 clocks (90kHz clocks ~ 178usec)
11=8 clocks (90kHz clocks ~ 89usec)
Bit[5] Opportunistic Mode Enable
0= Opportunistic Mode Disabled. Update Tach Reading once per PWMx Update Period (see Bits[1:0]
in this register)
1=Opportunistic Mode is Enabled. The tachometer reading register is updated any time a valid
tachometer reading can be made without stretching the PWM output signal. If a valid reading is
detected prior to the Update cycle, then the Update counter is reset.
Bit[7:6] Reserved
Register 97h:
stretching is disabled, the tach will only be monitored when the PWM duty cycle is ‘ON’. For
a complete definition of stretching see section
SMSC Test Register
PWM1 Option
PWM2 Option
PWM3 Option
Register Name
Register
Name
SMSC Test Register
(MSb)
Bit 7
RES
RES
RES
(MSb)
TST7
Bit 7
DATASHEET
Bit 6
RES
RES
RES
TST6
Bit 6
75
Bit 5
OPP
OPP
OPP
TST5
Bit 5
GRD1
GRD1
GRD1
Bit 4
PWM Stretching on page
TST4
Bit 4
GRD0
GRD0
GRD0
Bit 3
TST3
Bit 3
SZEN
SZEN
SZEN
Bit 2
TST2
Bit 2
UPDT1
UPDT1
UPDT1
Bit 1
TST1
Bit 1
38.
Revision 0.4 (09-25-07)
UPDT0
UPDT0
UPDT0
(LSb)
Bit 0
(LSb)
TST0
Bit 0
Default
Default
Value
Value
0Ch
0Ch
0Ch
5Ah
If