EMC6D102-CZC-TR Standard Microsystems (SMSC), EMC6D102-CZC-TR Datasheet
EMC6D102-CZC-TR
Specifications of EMC6D102-CZC-TR
Related parts for EMC6D102-CZC-TR
EMC6D102-CZC-TR Summary of contents
Page 1
... Supports 4 programmable temperature averaging modes — 2 monitoring modes: Continuous or Cycle (Power Saving mode) — Offers 2 Low Power Modes when monitoring is off: Sleep and Shutdown SMSC EMC6D102 EMC6D102 Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features Voltage Monitor — ...
Page 2
... EMC6D102-CZC FOR 24 PIN SSOP LEAD-FREE ROHS COMPLIANT PACKAGE EMC6D102-CZC-TR FOR 24 PIN SSOP LEAD-FREE ROHS COMPLIANT PACKAGE 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2007 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given ...
Page 3
... Stretching the SCLK Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.8 SMBus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.9 Bus Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.10 SMBus Alert Response Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Chapter 5 Hardware Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 Input Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2 Resetting the EMC6D102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2.2 Soft Reset (Initialization 5.3 Monitoring Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.3.1 Continuous Monitoring Mode 5.3.2 Cycle Monitoring Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 ...
Page 4
... Register 97h: SMSC Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.2.43 Register 98h:SMSC Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.2.44 Register FFh: SMSC Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Chapter 8 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 8.1 Maximum Guaranteed Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 8.2 Ratings for Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Revision 0.4 (09-25-07) Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features 4 DATASHEET Datasheet SMSC EMC6D102 ...
Page 5
... Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features Datasheet Chapter 9 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 9.1 PWM Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 9.2 SMBus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Chapter 10 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Appendix A ADC Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Appendix B Example Fan Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 SMSC EMC6D102 5 DATASHEET Revision 0.4 (09-25-07) ...
Page 6
... List of Figures Figure 2.1 EMC6D102 Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 4.1 Address Selection on EMC6D102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 5.1 Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 6.1 Automatic Fan Control Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 6.2 Automatic Fan Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 6.3 Spin Up Reduction Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 6.4 Illustration of PWM Ramp Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 6.5 PWM and Tachometer Concept Figure 7 ...
Page 7
... Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features Datasheet List of Tables Table 3.1 EMC6D102 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 3.2 Buffer Type Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 4.1 SMBus Slave Address Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 4.2 SMBus Write Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 4.3 SMBus Read Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 4 ...
Page 8
... Chapter 1 General Description The EMC6D102 is an environmental monitoring device with automatic fan control capability. This ACPI compliant device provides hardware monitoring for up to five voltages and three thermal zones, measures the speed four fans, and controls the speed of multiple DC fans using Pulse Width Modulator (PWM) outputs ...
Page 9
... Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features Datasheet Chapter 2 Pinout This Environmental Monitoring and Control device (EMC) is offered pin SSOP mechanical package. The EMC6D102 pin SSOP. SDA 1 2 SCL 3 VSS 4 VCC 5 VID0 6 VID1 7 VID2 8 VID3 9 TACH3/INT# 10 PWM2/INT# ...
Page 10
... Analog input for +2.5V Vccp Analog input for +Vccp (processor voltage 3.0V). 12V_IN Analog input for +12V Revision 0.4 (09-25-07) Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features Table 3.1 EMC6D102 Pin Description BUFFER TYPE HARDWARE MONITORING BLOCK (24) I OD3 M I ...
Page 11
... Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features Datasheet Table 3.1 EMC6D102 Pin Description (continued) NAME FUNCTION TACH1 Input for monitoring a fan tachometer input. TACH2 Input for monitoring a fan tachometer input. TACH3 Input for monitoring a fan tachometer input. ...
Page 12
... Operation, 5V Tolerance The EMC6D102 is intended to operate with a nominal 3.3V power supply. The analog voltage pins are connected to voltage sources at their respective nominal levels. All digital signal pins are 3V switching, but are tolerant to 5V. Revision 0.4 (09-25-07) Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features ...
Page 13
... Address Enable# pulled to ground through 10kΩ resistor Address Select pulled to VCC through a 10kΩ resistor In this way, there can three EMC6D102 devices on the SMBus at any time. Multiple EMC6D102 devices can be used to monitor additional processors and temperature zones. SMSC EMC6D102 Table 4.1 SMBus Slave Address Options ...
Page 14
... Figure 4.1 Address Selection on EMC6D102 4.2 Slave Bus Interface The EMC6D102 device SMBus implementation is a subset of the SMBus interface to the host. The device is a slave-only SMBus device. The implementation in the device is a subset of SMBus since it only supports four protocols. The Write Byte and Read Byte protocols are valid SMBus protocols for the device. This part responds to other protocols as described in the Invalid Protocol Section ...
Page 15
... Undefined Registers Reads to undefined registers return 00h. Writes to undefined registers have no effect and return no error. 4.5 General Call Address Response The EMC6D102 will not respond to a general call address of 0000_000. SMSC EMC6D102 Table 4.2 SMBus Write Byte Protocol WR ACK REG. ADDR ...
Page 16
... The EMC6D102 device, which pulled SMBALERT# low, will acknowledge the Alert Response Address and respond with its device address. The 7-bit device address provided by the EMC6D102 device is placed in the 7 most significant bits of the byte. The eighth bit can be a zero or one. ...
Page 17
... Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features Datasheet Note: The INT# signal is an alternate function on the PWM2 and TACH3 pins. The EMC6D102 device will respond to the SMBus Alert Response address even if the INT# signal is not selected as the alternate function on one of these pins as long as the following conditions exist: the INTEN bit (register 7Ch bit 2) is set, an individual status bit is set in one of the interrupt status registers, and the corresponding group enable bit is set ...
Page 18
... Input Monitoring The EMC6D102 device’s monitoring function is started by writing a ‘1’ to the START bit in the Ready/Lock/Start Register (0x40). Measured values from the analog inputs and temperature sensors are stored in Reading Registers. The values in the reading registers can be accessed via the SMBus interface ...
Page 19
... In the continuous monitoring mode, the sampling and conversion process is performed continuously for each voltage and temperature reading after the Start bit is set high. The time for each voltage and temperature reading is shown above for each measurement option. SMSC EMC6D102 Table 5.1 AVG[2:0] Bit Decoder MEASUREMENTS PER READING ...
Page 20
... Sampling of all values occurs in a nominal 223 ms (default - see 19). Table 5.3 ADC Conversion Sequence Remote Diode Temp Reading 1 Ambient Temperature reading VCC reading +12V reading +5V reading +2.5V reading Vccp (processor) reading Remote Diode Temp Reading 2 19). Each measured value is compared to values stored 30. 30. 20 DATASHEET Datasheet REGISTER SMSC EMC6D102 Auto ...
Page 21
... Each interrupt status bit has a corresponding bit located in an interrupt enable register, which may be used to enable/disable the individual event from setting the status bit. See the figure below for the status and enable bits used to control the interrupt bits and INT# pin. SMSC EMC6D102 and on page 55. These registers are used to reflect the state of all temperature, Chapter 7, " ...
Page 22
... Diode Fault on page 5.4.1 Diode Fault The EMC6D102 Chip automatically sets the associated diode fault bit to 1 when any of the following conditions occur on the Remote Diode pins: The positive and negative terminal are an open circuit. Positive terminal is connected to VCC Positive terminal is connected to ground Negative terminal is connected to VCC Revision 0 ...
Page 23
... VCCP_Error_En, 25V_Error_En, 18V_Error_En, and/or 15V_Error_En), group enable (VOLT_EN), and global enable (INT_EN)). This pin will remain low while the associated voltage error bit in the Interrupt Status Register 1 or Interrupt Status Register 2 is set. SMSC EMC6D102 on page 68. 22. The following description assumes that the interrupt enable bits for all ...
Page 24
... Since any of these inputs can be Revision 0.4 (09-25-07) Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features Table 5.4 Low Power Mode Control Bits DESCRIPTION Sleep Mode Shutdown Mode Monitoring 24 DATASHEET Datasheet 16. SMSC EMC6D102 ...
Page 25
... Remote Diode 1 (D1) or Remote Diode 2 (D2) status bits will be set in the Interrupt Status Register 1. If auto fan option is selected, the hardware will adjust the operation of the fans accordingly. See Fan Control Operating Mode on page SMSC EMC6D102 83. Table 5.5 Min/Max ADC Conversion Table + ...
Page 26
... READING (HEX) -127 81h -50 CEh -25 E7h -1 FFh 0 00h 1 01h 25 19h 50 32h 127 7Fh 128 80h 26 DATASHEET Datasheet 0 C. DIGITAL OUTPUT 1000 0001 1100 1110 1110 0111 1111 1111 0000 0000 0000 0001 0001 1001 0011 0010 0111 1111 1000 0000 SMSC EMC6D102 ...
Page 27
... Thermal Zones Each temperature measurement input is assigned to a Thermal Zone to control the PWM outputs in Auto Fan Control mode. These zone assignments are as follows: Zone 1 = Remote Diode 1 (Processor) Zone 2 = Ambient (Internal) Temperature Sensor Zone 3 = Remote Diode 2 SMSC EMC6D102 27 DATASHEET Revision 0.4 (09-25-07) ...
Page 28
... Regardless of all changes made by the BIOS to the limit and parameter registers during configuration, the EMC6D102 will continue to operate based on default values until the Start bit, in the Ready/Lock/Start register, is set. Once the Start bit is set, the EMC6D102 will operate according to the values that were set by BIOS in the limit and parameter registers ...
Page 29
... PWM duty cycle. The operation of the fans can be monitored based on reading the temperature and tachometer reading registers and/or by polling the interrupt status registers. The EMC6D102 offers the option of generating an interrupt indicated by the INT# signal located on the PWM2 and TACH3 pins. ...
Page 30
... Auto Fan Control Operating Mode The EMC6D102 implements automatic fan control. In Auto Fan Mode, this device automatically adjusts the PWM duty cycle of the PWM outputs, according to the flow chart on the following page (see Figure 6.1 Automatic Fan Control Flow Diagramon page PWM outputs are assigned to a thermal zone based on the PWMx Configuration registers (see 5.10, " ...
Page 31
... Zone x Low Temp Limit registers. This value will prevent the fan from oscillating between on and off if the temperature is around the minimum temperature limit. This value is programmed in Registers 6Dh-6Eh: Zone Hysteresis registers. SMSC EMC6D102 Auto Fan Mode Initiated End Polling ...
Page 32
... Revision 0.4 (09-25-07) Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features shows the control for the auto fan algorithm. The part allows a minimum 32 DATASHEET Datasheet SMSC EMC6D102 ...
Page 33
... Note that more than one tachometer may be associated with a PWM, in which case all tachometers associated with a PWM must be in the valid range for spin-up to end. SMSC EMC6D102 MIN/OFF bit = 1 (Fan stays on when temperature is below minimum) ...
Page 34
... If the current PWM duty cycle is equal to the calculated duty cycle the PWM output will remain unchanged. Revision 0.4 (09-25-07) Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features duty cycle = 100% tach reading > tach reading < tach limit tach limit Spin Up Time Programmed Spin Up Time Figure 6.3 Spin Up Reduction Enabled 34 DATASHEET Datasheet SMSC EMC6D102 ...
Page 35
... SMSC EMC6D102 62). The actual duty cycle output is changed once per the period of the 36.) Table 5.2, “Conversion Cycle Timing,” on page Table 6.1 PWM Ramp Rate PWM RAMP TIME (SEC) (TIME FROM 0% DUTY PWM STEP ...
Page 36
... DATASHEET Datasheet TIME PER PWM PWM STEP RAMP (PWM STEP SIZE = RATE 1/255) (HZ) 10 msec 100 5 msec 200 73h 74h 73h 73h 74h 73h 74h 74h 11.4ms 11.4ms 11.4ms 11.4ms 73h 74h 74h SMSC EMC6D102 ...
Page 37
... Tach Reading register will be set to FFFFh. If one or more edges are detected, but less than the programmed number of edges, a slow fan event has occurred SMSC EMC6D102 In this mode, the fan tachometer simply counts the number of 90kHz ...
Page 38
... The associated PWM output will continue to stretch until all tachs that are associated with it have taken a measurement. Revision 0.4 (09-25-07) Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features 43.) 40) 38 DATASHEET Datasheet Linking Fan Summary of Operation SMSC EMC6D102 ...
Page 39
... FFFFh indicates that the fan is not spinning, or the tachometer input is not connected to a valid signal (This could be triggered by a counter overflow). The Tachometer registers are read only – a write to these registers has no effect. Mode 1 should be enabled and the tachometer limit register should be set to FFFFh if a tachometer input is left unconnected. SMSC EMC6D102 PWM “ON” ...
Page 40
... If the programmed number of edges occurs during the PWM ‘ON’ time or stretching time: latch the tachometer count and stop stretching PWM (see Note below). Revision 0.4 (09-25-07) Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features 40 DATASHEET Datasheet SMSC EMC6D102 ...
Page 41
... TIME) 25% (HZ) (MSEC) (MSEC) 87.7 2.85 58.6 4.27 44 5.68 35.2 7.1 SMSC EMC6D102 below Table 6.2 for the one exception to this behavior. MAXIMUM TACHOMETER COUNT AT END OF PERIOD FFFFh FFFFh MINIMUM RPM AT DUTY CYCLE 100% 50% (MSEC) (Note 6.3) 25% 5 ...
Page 42
... Revolution 42 DATASHEET Datasheet (Note 6.4) (30/T ) TachPulse 50% 100% 1768 885 1319 661 878 440 661 332 = TachPulse (Note 6.6) (30/T ) TachPulse 50% 100% 2673 1331 1777 887 1331 665 1063 532 884 442 660 330 439 220 331 166 = TachPulse SMSC EMC6D102 ...
Page 43
... TACH input is operating within normal parameters. (Note: SUREN bit is located in the Configuration Register at offset 7Fh measure the tachometer input in Mode 2, the tachometer logic must know when the associated PWM is ‘ON’. SMSC EMC6D102 MINIMUM RPM AT STRETCHED PULSE WIDTH 100MSEC 200MSEC ...
Page 44
... Inhibit fan tachometer interrupts when the associated PWM is ‘OFF’. See the description of the PWM_TACH register. The default configuration is: PWM1 -> TACH1. PWM2 -> TACH2. PWM3 -> TACH3 & TACH4. Revision 0.4 (09-25-07) Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features 44 DATASHEET Datasheet SMSC EMC6D102 ...
Page 45
... R/W Remote Diode 1 Low Temp 4Fh R/W Remote Diode 1 High Temp 50h R/W Internal Low Temp 51h R/W Internal High Temp 52h R/W Remote Diode 2 Low Temp SMSC EMC6D102 Table 7.1 Register Summary Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 MSb ...
Page 46
... VOLT ECh Yes RES P2INT T3INT 10h Yes TACH2 TACH1 TACH 1Eh Yes T2L T1H T1L A4h Yes D1EN AMB TEMP 0Eh Yes RES RES RES 00h No RES RES RES 00h No RD1.2 RD1.1 RD1.0 N/A No AM.2 AM.1 AM.0 N/A No SMSC EMC6D102 ...
Page 47
... Undefined Registers The registers shown in the table above are the defined registers in the part. Any reads to undefined registers always return 00h. Writes to undefined registers have no effect and do not return an error. SMSC EMC6D102 Table 7.1 Register Summary (continued) Bit 7 Bit 6 Bit 5 ...
Page 48
... Bit 7 Bit 6 Bit 5 Bit 4 (MSb DATASHEET Datasheet Bit 0 Default Bit 3 Bit 2 Bit 1 (LSb) Value TST3 TST2 TST1 TST0 00h Bit 0 Default Bit 3 Bit 2 Bit 1 (LSb) Value 00h 00h 00h Bit 0 Default Bit 3 Bit 2 Bit 1 (LSb) Value N/A SMSC EMC6D102 ...
Page 49
... C0h +5V 5.0V C0h +12V 12.0V C0h The Voltage Reading registers will be updated automatically by the EMC6D102 Chip with a minimum frequency of 4Hz. These registers are read only – a write to these registers has no effect. 7.2.4 Registers 25-27h: Temperature Reading Register Read/ Register Name Address ...
Page 50
... Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features READING (DEC) -127 . . . - 127 Bit 7 Bit 6 Bit 5 Bit 4 (MSb DATASHEET Datasheet READING (HEX) 81h . . . CEh . . . 00h . . . 32h . . . 7Fh 80h Bit 0 Default Bit 3 Bit 2 Bit 1 (LSb) Value N/A SMSC EMC6D102 ...
Page 51
... In manual mode, when the start bit is set to 1 and the lock bit is 0, the current duty cycle registers are writeable to control the PWMs. Note: When the lock bit is set to 1, the current duty cycle registers are Read-Only. SMSC EMC6D102 Bit 7 Bit 6 ...
Page 52
... Version / Stepping The four least significant bits of the Version / Stepping register [3:0] contain the current stepping of the EMC6D102 silicon. The four most significant bits [7:4] reflect the version number. The register is used by application software to identify which device has been implemented in the given system ...
Page 53
... This register bit becomes read only once it is set. The EMC6D102 sets this bit automatically after the part is fully powered up, has completed the power-up-reset process, and after all A/D converters are functioning (all bias conditions for the A/Ds have stabilized and the A/Ds are in operational mode). (Always reads back ‘ ...
Page 54
... Note below). The contents of this register are cleared (set to 0) automatically by the EMC6D102 after it is read by software, if the voltage or temperature no longer violates the limits set in the limit and parameter registers. Once set, the Interrupt Status Register 1 bits remain set until a read event occurs or until the individual enable bits is cleared, even if the voltage or temperature no longer violate the limits set in the limit and parameter registers ...
Page 55
... Note below). The contents of this register are cleared (set to 0) automatically by the EMC6D102 after it is read by software, if the voltage no longer violate the limits set in the limit and parameter registers, if the temperature sensor error no loner exists the tach reading register is no longer above the minimum ...
Page 56
... R VID0-4 The VID register contains the values of EMC6D102 VID0-VID4 input pins. This register indicates the status of the VID lines that interconnect the processor to the Voltage Regulator Module (VRM). Software uses the information in this register to determine the voltage that the processor is designed to operate at ...
Page 57
... EMC6D102 in the interrupt status registers (41-42h). Voltages are presented in the registers at ¾ full scale for the nominal voltage, meaning that at nominal voltage, each input will be C0h, as shown in Table 7 ...
Page 58
... EMC6D102 in the Interrupt Status Register 1 (41h). For example, if the temperature reading from the Remote1- and Remote1+ inputs exceeds the Remote Diode 1 High Temp register limit setting, Bit[ the Interrupt Status Register 1 will be set. The temperature limits in these registers are represented as 8 bit, 2’ ...
Page 59
... Bit [4] inverts the PWM output. If set to 1, 100% duty cycle will yield an output that is low for 255 clocks and high for 1 clock. If set to 0, 100% duty cycle will yield an output that is high for 255 clocks and low for 1 clock. SMSC EMC6D102 Bit 7 Bit 6 ...
Page 60
... Bit 5 Bit 4 (MSb) RAN3 RAN2 RAN1 RAN0 RAN3 RAN2 RAN1 RAN0 RAN3 RAN2 RAN1 RAN0 60 DATASHEET Datasheet Bit 0 Default Bit 3 Bit 2 Bit 1 (LSb) Value RES FRQ2 FRQ1 FRQ0 C3h RES FRQ2 FRQ1 FRQ0 C3h RES FRQ2 FRQ1 FRQ0 C3h SMSC EMC6D102 ...
Page 61
... Table 7.9 Register Setting vs. PWM Frequency FREQ[2:0] 000 001 010 011 100 101 110 111 Range Selection (Default =1100=32×C) SMSC EMC6D102 PWM Duty is linear over this range Temperature LIMIT: PWM output at MIN FAN SPEED PWM FREQUENCY 11.0 Hz 14.6 Hz 21.9 Hz 29 ...
Page 62
... OFF3 OFF2 OFF1 RES RR2E RR2-2 RR2-1 RR2-0 PWM ACTION At 0% duty below LIMIT At Min PWM Duty below LIMIT 62 DATASHEET Datasheet Bit 0 Default Bit 3 Bit 2 Bit 1 (LSb) Value RR1E RR1-2 RR1-1 RR1-0 00h RR3E RR3-2 RR3-1 RR3-0 00h SMSC EMC6D102 ...
Page 63
... R/W PWM3 Minimum Duty Cycle These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have no effect. SMSC EMC6D102 Table 7.12. For a description of the Ramp Rate Control logic see 34. Table 7.12 PWM Ramp Rate Control ...
Page 64
... Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features Table 7.13 PWM Duty vs. Register Setting VALUE (DECIMAL 128 . . . 255 Bit 7 Bit 6 Bit 5 (MSb DATASHEET Datasheet VALUE (HEX) 00h . . . 40h . . . 80h . . . FFh Bit 0 Default Bit 4 Bit 3 Bit 2 Bit 1 (LSb) Value SMSC EMC6D102 5Ah 5Ah 5Ah ...
Page 65
... In this case, the absolute limit can be chosen to be 7Fh for those zones that are not associated with a fan, so that the fans won't turn on unless the temperature hits 127 degrees. SMSC EMC6D102 LIMIT (DEC) -127 ...
Page 66
... Table 7.16 Hysteresis Settings SETTING HYSTERESIS 0h 0° 5° 15°C 66 DATASHEET Datasheet ABS LIMIT (HEX) 81h . . . CEh . . . 00h . . . 32h . . . 7Fh Bit 0 Default Bit 4 Bit 3 Bit 2 Bit 1 (LSb) H1-0 H2-3 H2-2 H2-1 H2-0 H3-0 RES RES RES RES SMSC EMC6D102 Value 44h 40h ...
Page 67
... R/W SMSC Test Register This is a read/write register. Writing this register may produce unwanted results. These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have no effect. SMSC EMC6D102 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 ...
Page 68
... AVG2 AVG1 AVG0 SMSC Table 7.17 AVG[2:0] Bit Decoder AVERAGES PER READING REM DIODE 2 INTERNAL DIODE 128 DATASHEET Datasheet Bit 0 Default Bit 3 Bit 2 Bit 1 (LSb) SMSC INTEN MONMD LPMD ALL VOLTAGE READINGS (+2.5V, +5V, +12V, VCCP, AND VCC SMSC EMC6D102 Value 40h ...
Page 69
... These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have no effect. This register contains the following bits: Bit[0] TACH3/INT# pin select: 0=TACH, 1=INT# Bit[1] PWM2/INT# pin select: 0=PWM, 1=INT# Bit[2] Reserved SMSC EMC6D102 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 ...
Page 70
... Revision 0.4 (09-25-07) Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 (MSb) RES RES RES TACH4 TACH3 70 DATASHEET Datasheet Bit 0 Default Bit 2 Bit 1 (LSb) Value TACH2 TACH1 TACH 1Eh SMSC EMC6D102 ...
Page 71
... These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have no effect. This register is used to enable individual thermal error events to set the corresponding status bits in the interrupt status registers. This register also contains the group thermal enable bit (Bit[0] TEMP), SMSC EMC6D102 22. Bit 7 Bit 6 ...
Page 72
... VCC.3 VCC.2 VCC.1 VCC.0 th per unit measured. (i.e., Temperature Range: 72 DATASHEET Datasheet Bit 0 Default Bit 3 Bit 2 Bit 1 (LSb) Value RD1.3 RD1.2 RD1.1 RD1.0 N/A AM.3 AM.2 AM.1 AM.0 N/A V25.3 V25.2 V25.1 V25.0 N/A VCP.3 VCP.2 VCP.1 VCP.0 N/A SMSC EMC6D102 ...
Page 73
... This register must not be written. Writing this register may produce unexpected results. 7.2.39 Registers 8Eh: SMSC Test Register Register Read/ Register Name Address Write 8Eh R SMSC Test Register SMSC EMC6D102 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 (MSb) TST7 TST6 TST5 TST4 TST3 ...
Page 74
... STCH1 STCH0 3EDG MODE STCH2 STCH1 STCH0 3EDG MODE STCH2 STCH1 STCH0 3EDG MODE 74 DATASHEET Datasheet Bit 0 Default Bit 3 Bit 2 Bit 1 (LSb) Value EDG1 EDG0 SLOW CCh EDG1 EDG0 SLOW CCh EDG1 EDG0 SLOW CCh EDG1 EDG0 SLOW CCh SMSC EMC6D102 ...
Page 75
... Update cycle, then the Update counter is reset. Bit[7:6] Reserved Register 97h: 7.2.42 Register Read/ Register Name Address Write 97h R/W SMSC Test Register SMSC EMC6D102 PWM Stretching on page Bit 7 Bit 6 Bit 5 Bit 4 (MSb) RES RES OPP GRD1 RES ...
Page 76
... SMSC Test Register Bit 7 Bit 6 Bit 5 Bit 4 (MSb) TST7 TST6 TST5 TST4 76 DATASHEET Datasheet Bit 0 Default Bit 3 Bit 2 Bit 1 (LSb) Value TST3 TST2 TST1 TST0 F1h glitch Bit 0 Default Bit 3 Bit 2 Bit 1 (LSb) Value TST3 TST2 TST1 TST0 N/A SMSC EMC6D102 ...
Page 77
... DC output. If this possibility exists suggested that a clamp circuit be used. 8.2 Ratings for Operation VCC=+3.3V±10% PARAMETER SYMBOL Temperature-to-Digital Converter Characteristics Internal Temperature Accuracy External Diode Sensor Accuracy SMSC EMC6D102 Refer to JEDEC Spec. J-STD-020 MIN TYP MAX UNITS ±0.25 C ...
Page 78
... IHI V 500 HYS 500 DATASHEET Datasheet UNITS COMMENTS Note 8.1 % LSB %/V sec Note 8.2 Note 8.3 msec kΩ 10 bits Note 8 +4.0 mA (Note V OL (Note 8. µ µA pF All outputs open, all inputs transitioning from/to 0V to/from 3.3V µA 3 µA SMSC EMC6D102 8.5) ...
Page 79
... The amount of averaging is programmable. The output of the averaging block produces a 12-bit temperature or voltage reading value. The 8 MSbits go to the reading register and the 4 LSbits to the A/D LSb register. SMSC EMC6D102 for conversion cycle timing for all 79 DATASHEET ...
Page 80
... Figure 9.1 PWMx Output Timing Table 9.1 Timing for PWM[1:3] Outputs MIN 11.4 9. During Spin-up the PWM High Time can reach a 100% or Full On. PWM t HIGH HD:DAT SU:DAT S Figure 9.2 SMBus Timing 80 DATASHEET Datasheet TYP MAX UNITS 90.9 msec 99 HD:STA SU:STO t SU:STA SMSC EMC6D102 , PWM P ...
Page 81
... Dec. 1998. Note 9.4 At 400kHz, spikes of a maximum pulse width of 50ns must be suppressed by the input filter. Note 9.5 If using 100 kHz clock frequency, the next data bit output to the SDA line will be 1250 ns (1000 ns (T SMSC EMC6D102 LIMITS MIN 10 1.3 0.6 0.6 ...
Page 82
... Overall Package Height 0.010 0.061 0.344 0.244 0.157 0.010 Lead Frame Thickness 0.050 o 8 0.012 0.004 82 DATASHEET Datasheet REMARKS Standoff Body Thickness X Body Size Y Span Y body Size Lead Foot Length Lead Pitch Lead Foot Angle Lead Width Coplanarity SMSC EMC6D102 ...
Page 83
... SMSC EMC6D102 V 2 <0.0172 <0.013 0.017–0.034 0.013–0.026 0.012–0.023 0.034–0.052 0.026–0.039 0.023–0.035 0.052–0.069 0.039– ...
Page 84
... Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features 4.331–4.348 3.281–3.294 2.951–2.964 4.348–4.366 3.294–3.307 2.964–2.975 4.366–4.383 3.307–3.320 2.975–2.987 >4.383 >3.320 84 DATASHEET Datasheet A/D OUTPUT 252 1111 1100 253 1111 1101 254 1111 1110 >2.988 255 1111 1111 SMSC EMC6D102 ...
Page 85
... PWMx 2.2k Figure B.1 Fan Drive Circuitry (Apply to PWM Driving Two Fans) PWMx Figure B.2 Fan Drive Circuitry (Apply to PWM Driving One Fan) SMSC EMC6D102 shows how the part can be used to control four fans by connecting two 3.3V MMBT3904 10 10 3.3V ...
Page 86
... Figure B.4 Remote Diode (Apply to Remote2 Lines) Notes: 1. 2.2nF cap is optional and should be placed close to the EMC6D102 if used. 2. The voltage at PWM3 must be at least 2.0V to avoid triggering Address Enable. 3. The Remote Diode + and Remote Diode - tracks should be kept close together, in parallel with grounded guard tracks on each side ...