EMC6D102-CZC-TR Standard Microsystems (SMSC), EMC6D102-CZC-TR Datasheet - Page 67

• Manufacturer Part Number: EMC6D102-CZC-TR
• Manufacturer: Standard Microsystems (SMSC)

Specifications of EMC6D102-CZC-TR

• Operating Current: 3mA
• Operating Temperature Classification: Commercial
• Package Type: SSOP
• Lead Free Status / Rohs Status: Compliant

Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features
Datasheet
SMSC EMC6D102
7.2.23
7.2.24
7.2.25
7.2.26
Register
Address
Register
Address
Register
Address
Register
Address
7Ah
6Fh
7Bh
79h
Read/
Write
Read/
/Write
Read/
Write
Read
Write
R/W
R/W
R
R/W
Register 6F: XOR Test Register
This register becomes read only when the Lock bit is set. Any further attempts to write to this register
shall have no effect.
The part incorporates an XOR tree test mode. When the test mode is enabled by setting the ‘XEN’ bit
high via SMBus, the part enters XOR test mode.
The following signals are included in the XOR test tree:
Since the test mode is XOR tree, the order of the signals in the tree is not important. SDA and SCL
are not included in the test tree.
Register 79h: SMSC Test Register
This is a read/write register. Writing this register may produce unwanted results.
This register becomes read only when the Lock bit is set. Any further attempts to write to this register
shall have no effect.
Register 7Ah: SMSC Test Register
This is a read/write register. Writing this register may produce unwanted results.
Register 7Bh: SMSC Test Register
This is a read/write register. Writing this register may produce unwanted results.
These registers become read only when the Lock bit is set. Any further attempts to write to these
registers shall have no effect.
VID0, VID1, VID2, VID3, VID4
TACH1, TACH2, TACH3, TACH4
PWM2, PWM3
SMSC Test Register
Register Name
SMSC Test Register
SMSC Test Register
Register Name
XOR Test Register
Register Name
Register Name
(MSb)
Bit 7
RES
(MSb)
TST7
DATASHEET
Bit 7
(MSb)
(MSb)
TST7
Bit 7
Bit 7
RES
TST6
Bit 6
TST6
67
Bit 6
TST6
Bit 6
Bit 6
RES
TST5
Bit 5
TST5
Bit 5
TST5
Bit 5
RES
Bit 5
TST4
Bit 4
TST4
Bit 4
TST4
Bit 4
Bit 4
RES
TST3
Bit 3
TST3
Bit 3
TST3
Bit 3
Bit 3
RES
TST2
TST2
Bit 2
Bit 2
TST2
Bit 2
Bit 2
RES
TST1
TST1
TST1
Bit 1
Bit 1
Bit 1
Bit 1
RES
Revision 0.4 (09-25-07)
(LSb)
(LSb)
TST0
(LSb)
Bit 0
Bit 0
TST0
(LSb)
TST0
XEN
Bit 0
Bit 0
Default
Default
Default
Default
Value
Value
Value
Value
00h
00h
00h
00h