GCIXP1240AB 837151 Intel, GCIXP1240AB 837151 Datasheet - Page 33

• Manufacturer Part Number: GCIXP1240AB 837151
• Manufacturer: Intel

Specifications of GCIXP1240AB 837151

• Lead Free Status / Rohs Status: Not Compliant

3.3.4
Datasheet
Table 15. IX Bus Interface Pins
IX Bus Interface Pins
FCLK
PORTCTL_L[3:0]
FPS[2:0]
FDAT[63:0]
IX Bus Signal
Names
[63]
[62]
[61]
[60]
[59]
[58]
[57]
[56]
[55]
[54]
[53]
[52]
[51]
[50]
[49]
[48]
[47]
[46]
[45]
[44]
[43]
[42]
[41]
[40]
[39]
[38]
[37]
[36]
[35]
[34]
[33]
[32]
[31]
[3]
[2]
[1]
[0]
[2]
[1]
[0]
AB30
AC30
AC31
AB29
AA28
AC29
AD31
AD30
AC28
AD29
AE31
AE30
AF31
AF30
AF29
AG31
AG30
AF28
AG29
AH31
AH30
AH27
AK28
AL28
AJ27
AH26
AK27
AL27
AJ26
AK26
AL26
AJ25
AH24
AK25
AL25
AJ24
AH23
AK24
AL24
AJ23
AK23
Pin #
I3
O1/TS 4
O4/TS 3
I2/O5/
TS
Type
1
64
Total
IX Bus Clock input. All IX Bus transfers are synchronized to this
clock. Typical operating frequency 33 MHz - 104 MHz.
Port Control outputs. Used to select the transmit and/or receive
mode for IX Bus devices, typically MAC devices.
In 64-bit bidirectional IX Bus mode, this is a 4-bit bus used to
indicate transmit or receive commands and device selects.
In 32-bit unidirectional IX Bus mode, bits [1:0] are used to select
the receive device and bits [3:2] are used to select the transmit
device.
In a shared IX Bus system, these pins will be tri-stated when
passing ownership of the IX Bus.
MAC Port Select outputs.
In 32-bit and 64-bit modes, these pins select one of eight MAC
receive ports from the selected MAC device. See IX Bus control
signal decode tables.
In a shared IX Bus system, these pins will be tri-stated when
passing ownership of the IX Bus.
IX Bus Data.
One 64-bit bus in bidirectional IX Bus mode.
Two 32-bit buses in unidirectional IX Bus mode where bits [63:32]
are used for Transmit Data output and [31:0] are used for Receive
Data input.
In a shared IX Bus system, these pins will be tri-stated when
passing ownership of the IX Bus.
Intel
Pin Descriptions
®
IXP1240 Network Processor
33