GCIXP1240AB 837151 Intel, GCIXP1240AB 837151 Datasheet - Page 120
GCIXP1240AB 837151
Manufacturer Part Number
GCIXP1240AB 837151
Description
Manufacturer
Intel
Datasheet
1.GCIXP1240AB_837151.pdf
(146 pages)
Specifications of GCIXP1240AB 837151
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Intel
4.3.7.5
4.3.8
4.3.8.1
120
Figure 60. IX Bus Ownership Passing
Figure 61. SRAM SCLK Signal AC Parameter Measurements
®
IXP1240 Network Processor
TK_IN/TK_OUT
The following timing diagrams show the transition from one IX Bus owner to another. Note that
prior to giving up the bus, the PORTCTL[4:0] signals are driven high which will not select any
ports. Then the signal is tri-stated and must be held up with pullup resistors.
SRAM Interface
SRAM SCLK Signal AC Parameter Measurements
Vt1 = 0.5*VDDX
Vt2 = 0.4*VDDX
Vt3 = 0.3*VDDX
A = Driven by the Intel
B = Driven high for one cycle by the IXP1200 Network Processor _L2 (no port is selected),
C = Weak external pull-up resistors are recommended on PORTCTL_L[7:0], FPS[2:0] and TXAXIS.
Notes:
if the transfer is a Rx.
then tristated.
(is TK_IN to _L2 )
PORTCTL_L[7:0]
TK_OUT _L1
TK_OUT _L2
FDAT[63:0]
FPS[2:0]
TXAXIS
FCLK
V
®
Device 1 Releases Token
t3
IXP1240 Network Processor _L1 if the transfer is a Tx, not driven
V
1
t2
V
t1
T
r
2
Data
T
high
3
T
T
cyc
4
f
B
A
5
T
low
C
Device 2 Now Has Token
6
7
8
9
Datasheet
A8904-01
A8608-01
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