EVAL-AD7266CB Analog Devices Inc, EVAL-AD7266CB Datasheet - Page 7

• Manufacturer Part Number: EVAL-AD7266CB
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD7266CB

• Lead Free Status / Rohs Status: Not Compliant

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions
Pin No.
1, 29
2
3
4, 20
5, 6, 19
7 to 12
13 to 18
21
22
23 to 25
26
27
REF SELECT
Mnemonic
DGND
REF SELECT
AV
D
D
AGND
V to V
V
RANGE
SGL/DIFF
A0 to A2
CS
SCLK
A1
B1
CAP
CAP
DD
D
DGND
AGND
AGND
to V
AV
CAP
A,
B
V
V
Figure 2. Pin Configuration (CP-32-2)
DD
A1
A2
A
B6
A6
1
2
3
4
5
6
7
8
Description
Digital Ground. This is the ground reference point for all digital circuitry on the AD7266. Both DGND pins should
connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential
and must not be more than 0.3 V apart, even on a transient basis.
Internal/External Reference Selection. Logic input. If this pin is tied to DGND, the on-chip 2.5 V reference is used as
the reference source for both ADC A and ADC B. In addition, Pin D A and Pin D
capacitors. If the REF SELECT pin is tied to a logic high, an external reference can be supplied to the AD7266
through the D
Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on the AD7266. The
AV and DV
transient basis. This supply should be decoupled to AGND.
Decoupling Capacitor Pins. Decoupling capacitors (470 nF recommended) are connected to these pins to
decouple the reference buffer for each respective ADC. Provided the output is buffered, the on-chip reference can
be taken from these pins and applied externally to the rest of a system. The range of the external reference is
dependent on the analog input range selected.
Analog Ground. Ground reference point for all analog circuitry on the AD7266. All analog input signals and any
external reference signal should be referred to this AGND voltage. All three of these AGND pins should connect to
the AGND plane of a system. The AGND and DGND voltages ideally should be at the same potential and must not
be more than 0.3 V apart, even on a transient basis.
Analog Inputs of ADC A. These may be programmed as six single-ended channels or three true differential analog
input channel pairs. See Table 6.
Analog Inputs of ADC B. These may be programmed as six single-ended channels or three true differential analog
input channel pairs. See Table 6.
Analog Input Range Selection. Logic input. The polarity on this pin determines the input range of the analog input
channels. If this pin is tied to a logic low, the analog input range is 0 V to V . If this pin is tied to a logic high when
CS goes low, the analog input range is 2 × V . See the Analog Input Selection section for details.
Logic Input. This pin selects whether the analog inputs are configured as differential pairs or single ended. A logic
low selects differential operation while a logic high selects single-ended operation. See the Analog Input
Selection section for details.
Multiplexer Select. Logic inputs. These inputs are used to select the pair of channels to be simultaneously
converted, such as Channel 1 of both ADC A and ADC B, Channel 2 of both ADC A and ADC B, and so on. The pair
of channels selected may be two single-ended channels or two differential pairs. The logic states of these pins
need to be set up prior to the acquisition time and subsequent falling edge of CS to correctly set up the
multiplexer for that conversion. See the Analog Input Selection section for further details and Table 6 for
multiplexer address decoding.
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7266
and framing the serial data transfer.
Serial Clock. Logic input. A serial clock input provides the SCLK for accessing the data from the AD7266. This clock
is also used as the clock source for the conversion process.
(Not to Scale)
PIN 1
INDICATOR
AD7266
TOP VIEW
DD
DD
CAP
voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a
A and/or D
24
23
22
21
20
19
18
17
A1
A2
SGL/DIFF
RANGE
D
AGND
V
V
B1
B2
CAP
B
CAP
B pins.
Rev. A | Page 7 of 28
REF
REF SELECT
D
DGND
AGND
AGND
AV
CAP
V
V
DD
A1
A2
A
CAP
Figure 3. Pin Configuration (SU-32-2)
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
9
REF
10 11 12 13 14 15 16
PIN 1
(Not to Scale)
TOP VIEW
AD7266
CAP
B must be tied to decoupling
24
23
22
21
20
19
18
17
A1
A2
SGL/DIFF
RANGE
D
AGND
V
V
B1
B2
CAP
B
AD7266