EVAL-AD7266CB Analog Devices Inc, EVAL-AD7266CB Datasheet - Page 22

• Manufacturer Part Number: EVAL-AD7266CB
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD7266CB

• Lead Free Status / Rohs Status: Not Compliant

AD7266
SERIAL INTERFACE
Figure 41 shows the detailed timing diagram for serial inter-
facing to the AD7266. The serial clock provides the conversion
clock and controls the transfer of information from the AD7266
during conversion.
The
The falling edge of CS puts the track-and-hold into hold mode,
at which point the analog input is sampled and the bus is taken
out of three-state. The conversion is also initiated at this point
and requires a minimum of 14 SCLKs to complete. Once 13
SCLK falling edges have elapsed, the track-and-hold goes back
into track on the next SCLK rising edge, as shown in
at Point B. If a 16 SCLK transfer is used, then two trailing zeros
appear after the final LSB. On the rising edge of
conversion is terminated and D
three-state. If
further 14 (or 16) SCLK cycles on D
Conversion B is output on D
Likewise, if
on D
is illustrated in Figure 42 where the case for D
this case, the D
32
occurs first.
nd
CS
SCLK falling edge or the rising edge of CS , whichever
OUT
signal initiates the data transfer and conversion process.
B, the data from Conversion A is output on D
D
SCLK
OUT
D
D
SCLK
CS
OUT
OUT
CS
A
CS
CS is not brought high but is instead held low for a
THREE-
STATE
A
B
OUT
is held low for a further 14 (or 16) SCLK cycles
THREE-
STATE
line in use goes back into three-state on the
t
2
2 LEADING
0
2 LEADING ZEROS
ZEROS
1
t
2
ZERO
t
0
3
1
OUT
t
3
0
OUT
A (followed by two trailing zeros).
2
DB11
A and D
OUT
2
A
DB11
3
A, the data from
DB10
Figure 42. Reading Data from Both ADCs on One D
OUT
A
3
DB10
4
B go back into
OUT
DB9
CS , the
A is shown. In
t
t
6
A
4
4
t
Figure 41. Serial Interface Timing Diagram
5
5
DB9
Figure 41
OUT
t
t
6
4
B. This
2 TRAILING ZEROS
t
5
14
7
ZERO
Rev. A | Page 22 of 28
DB8
t
7
15
ZERO
2 LEADING ZEROS
16
A minimum of 14 serial clock cycles are required to perform
the conversion process and to access data from one conversion
on either data line of the AD7266.
leading zero to be read in by the microcontroller or DSP. The
remaining data is then clocked out by subsequent SCLK falling
edges, beginning with a second leading zero. Thus, the first
falling clock edge on the serial clock has the leading zero
provided and also clocks out the second leading zero. The 12-bit
result then follows with the final bit in the data transfer valid on
the 14
(13
possible to read in data on each SCLK rising edge depending on
the SCLK frequency. The first rising edge of SCLK after the
falling edge would have the second leading zero provided, and
the 13
Note that with fast SCLK values, and thus short SCLK periods,
in order to allow adequately for t
occur before the first SCLK falling edge. This rising edge of
SCLK may be ignored for the purposes of the timing
descriptions in this section. If a falling edge of SCLK is coincident
with the falling edge of
acknowledged by the AD7266, and the next falling edge of
SCLK will be the first registered after the falling edge of
ZERO
DB2
th
) falling edge. In applications with a slower SCLK, it may be
th
th
17
ZERO
OUT
falling edge, having being clocked out on the previous
rising SCLK edge would have DB0 provided.
t
5
Line with 32 SCLKs
DB1
DB11
13
B
B
t
DB0
8
CS , then this falling edge of SCLK is not
ZERO
THREE-STATE
2 TRAILING ZEROS
2
t
, an SCLK rising edge may
QUIET
CS going low provides the
ZERO
t
9
32
t
10
THREE-
STATE
CS .
CS