EVAL-AD7266CB Analog Devices Inc, EVAL-AD7266CB Datasheet - Page 25

• Manufacturer Part Number: EVAL-AD7266CB
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD7266CB

• Lead Free Status / Rohs Status: Not Compliant

AD7266 TO DSP563xx
The connection diagram in Figure 46 shows how the AD7266
can be connected to the ESSI (synchronous serial interface) of
the DSP563xx family of DSPs from Motorola. There are two
on-board ESSIs, and each is operated in synchronous mode
(Bit SYN = 1 in CRB register) with internally generated word
length frame sync for both TX and RX (Bit FSL1 = 0 and
Bit FSL0 = 0 in CRB).
Normal operation of the ESSI is selected by making MOD = 0
in the CRB. Set the word length to 16 by setting Bit WL1 = 1
and Bit WL0 = 0 in CRA.
To implement the power-down modes on the AD7266, the
word length can be changed to 8 bits by setting Bit WL1 = 0 and
Bit WL0 = 0 in CRA. The FSP bit in the CRB should be set to 1
so the frame sync is negative. It is imperative for signal
processing applications that the frame synchronization signal
from the DSP563xx provides equidistant sampling.
Rev. A | Page 25 of 28
In the example shown in Figure 46, the serial clock is taken
from the ESSI0 so the SCK0 pin must be set as an output,
SCKD = 1, while the SCK1 pin is set as an input, SCKD = 0. The
frame sync signal is taken from SC02 on ESSI0, so SCD2 = 1,
while on ESSI1, SCD2 = 0; therefore, SC12 is configured as an
input. The V
voltage as that of the DSP563xx. This allows the ADC to operate
at a higher voltage than its serial interface and therefore, the
DSP563xx, if necessary.
1
ADDITIONAL PINS OMITTED FOR CLARITY.
AD7266
Figure 46. Interfacing the AD7266 to the DSP563xx
DRIVE
D
D
V
1
SCLK
OUT
OUT
DRIVE
pin of the AD7266 takes the same supply
CS
A
B
SCK0
SCK1
SRD0
SRD1
SC02
SC12
DSP563xx
V
DD
AD7266
1