DAC1005D650HW/C1,5 NXP Semiconductors, DAC1005D650HW/C1,5 Datasheet - Page 18

• Manufacturer Part Number: DAC1005D650HW/C1,5
• Description: IC DAC 10BIT 650MSPS DL 100HTQFP
• Manufacturer: NXP Semiconductors

Specifications of DAC1005D650HW/C1,5

• Settling Time: 20ns
• Number Of Bits: 10
• Data Interface: SPI™
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 1.4W
• Operating Temperature: -45°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935286776518

NXP Semiconductors
DAC1005D650
Product data sheet
Table 11.
Default settings are shown highlighted.
Table 12.
Default settings are shown highlighted.
Table 13.
Table 14.
Bit
4 to 2 MODULATION[2:0]
1 to 0 INTERPOLATION[1:0] R/W
Bit
7
5
4 to 3 PLL_DIV[1:0]
2 to 1 PLL_PHASE[1:0]
0
Bit
7 to 0 FREQ_NCO[7:0]
Bit
7 to 0 FREQ_NCO[15:8]
Symbol
Symbol
PLL_PD
PLL_DIV_PD
PLL_POL
Symbol
Symbol
TXCFG register (address 01h) bit description
PLLCFG register (address 02h) bit description
FREQNCO_LSB register (address 03h) bit description
FREQNCO_LISB register (address 04h) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 3 September 2010
Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating
Access Value Description
R/W
Access
R/W
R/W
R/W
R/W
R/W
Access Value Description
R/W
Access Value Description
R/W
000
001
010
011
100
01
10
11
-
-
Value Description
0
1
0
1
00
01
10
00
01
10
0
1
modulation
interpolation
lower 8 bits for the NCO frequency setting
lower intermediate 8 bits for the NCO
frequency setting
dual DAC: no modulation
positive upper single sideband
up-conversion
positive lower single sideband up-conversion
negative upper single sideband up-conversion
negative lower single sideband up-conversion
f
f
f
PLL
PLL divider
PLL divider factor
PLL phase shift of f
DAC clock edge
s
s
s
= 2f
= 4f
= 8f
switched on
switched off
switched on
switched off
f
f
fs = 8 ¥ fclk
0×
120°
240°
normal
inverted
s
s
= 2 × f
= 4 × f
clk
clk
clk
…continued
clk
clk
DAC1005D650
s
© NXP B.V. 2010. All rights reserved.
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