EVAL-AD7763EBZ Analog Devices Inc, EVAL-AD7763EBZ Datasheet - Page 5

• Manufacturer Part Number: EVAL-AD7763EBZ
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD7763EBZ

• Lead Free Status / Rohs Status: Supplier Unconfirmed

TIMING SPECIFICATIONS
AV
Table 3.
Parameter
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
MCLK
ICLK
1
2
3
3A
3B
4
4A
4B
5
6
7
8
9
10
11
12
13
14
15
t
SCO frequency selected by SCR and CDIV pins.
t
All edges mentioned refer to SCP = 0. Invert SCO edges for SCP = 1.
In decimate × 32 mode, this time specification applies only when CDIV = 0 and SCR =1. For all other combinations of CDIV and SCR in decimate × 32 mode, the FSO
signal is constantly logic low.
1
4
1
5
ICLK
SCO
4
4, 5
4, 5
4
DD1
= t
= 1/f
1
= DV
+ t
ICLK
2
.
.
DD
= V
DRIVE
Limit at T
1
40
500
20
1 × t
1 × t
t
2
3
32 × t
1
2
6.5
5
0.5 × t
16 × t
t
5.5
1 × t
12
10
12
16 × t
SCO
SCO
= 2.5 V, AV
3
3
ICLK
ICLK
SCO
SCO
SCO
SCO
SCO
3
or 0.5 × t
or 0.5 × t
3
3
3
3
MIN
, T
DD2
MAX
ICLK
ICLK
= AV
2
2
DD3
= AV
DD4
Unit
MHz min
MHz max
kHz min
MHz max
typ
typ
typ
ns typ
ns typ
typ
ns typ
ns typ
ns max
ns max
ns min
typ
typ
ns max
min
ns min
ns min
ns min
typ
= 5 V, T
Rev. 0 | Page 5 of 32
A
= 25°C, normal mode, unless otherwise noted.
Description
Applied master clock frequency
Internal modulator clock derived from MCLK
SCO high period
SCO low period
DRDY low period
SCO rising edge to DRDY falling edge
SCO rising edge to DRDY rising edge
FSO low period
SCO rising edge to FSO falling edge
SCO falling edge to FSO rising edge
SDO valid after SCO falling edge
DRDY rising edge to SDL falling edge
SDL pulse width
FSI low period
FSI setup time
SDL falling edge to SDL falling edge
Initial data access time
SCO rising edge to SDO valid
SDO three-state to SCO rising edge
SDI setup time
SDI hold time
AD7763