EVAL-AD7763EBZ Analog Devices Inc, EVAL-AD7763EBZ Datasheet

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EVAL-AD7763EBZ

Manufacturer Part Number
EVAL-AD7763EBZ
Description
Manufacturer
Analog Devices Inc
Datasheet

Specifications of EVAL-AD7763EBZ

Lead Free Status / Rohs Status
Supplier Unconfirmed
FEATURES
120 dB dynamic range at 78 kHz output data rate
109 dB dynamic range at 625 kHz output data rate
112 dB SNR at 78 kHz output data rate
107 dB SNR at 625 kHz output data rate
625 kHz maximum fully filtered output word rate
Programmable oversampling rate (32× to 256×)
Flexible serial interface
Fully differential modulator input
On-chip differential amplifier for signal buffering
Low-pass finite impulse response (FIR) filter with default
Overrange alert bit
Digital offset and gain correction registers
Low power and power-down modes
Synchronization of multiple devices via SYNC pin
I
APPLICATIONS
Data acquisition systems
Vibration analysis
Instrumentation
GENERAL DESCRIPTION
The AD7763 high performance, 24-bit, Σ-Δ analog-to-digital
converter (ADC) combines wide input bandwidth and high
speed with the benefits of Σ-Δ conversion, as well as performance
of 107 dB SNR at 625 kSPS, making it ideal for high speed data
acquisition. A wide dynamic range, combined with significantly
reduced antialiasing requirements, simplifies the design process.
An integrated buffer to drive the reference, a differential ampli-
fier for signal buffering and level shifting, an overrange flag,
internal gain and offset registers, and a low-pass, digital FIR
filter make the AD7763 a compact, highly integrated data
acquisition device requiring minimal peripheral component
selection. In addition, the device offers programmable
decimation rates and a digital FIR filter, which can be user-
programmed to ensure that its characteristics are tailored for the
user’s application. The AD7763 is ideal for applications demanding
high SNR without necessitating the design of complex, front-
end signal processing.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
2
S interface mode
or user-programmable coefficients
with On-Chip Buffers, Serial Interface
24-Bit, 625 kSPS, 109 dB Σ-Δ ADC
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
MCLKGND
The differential input is sampled at up to 40 MSPS by an analog
modulator. The modulator output is processed by a series
of low-pass filters, the final filter having default or user-
programmable coefficients. The sample rate, filter corner
frequencies, and output word rate are set by a combination of
the external clock frequency and the configuration registers of
the AD7763.
The reference voltage supplied to the AD7763 determines the
analog input range. With a 4 V reference, the analog input range
is ±3.2 V differential-biased around a common mode of 2 V.
This common-mode biasing can be achieved using the on-chip
differential amplifiers, further reducing the external signal
conditioning requirements.
The AD7763 is available in an exposed paddle, 64-lead TQFP_EP
and is specified over the industrial temperature range from
−40°C to +85°C.
Table 1. Related Devices
Part No.
AD7760
AD7762
REFGND
ADR2:0
RESET
V
MCLK
SH2:0
SYNC
CDIV
REF+
FUNCTIONAL BLOCK DIAGRAM
BUF
Description
24-bit, 2.5 MSPS, 100 dB Σ-Δ, parallel interface
24-bit, 625 kSPS, 109 dB Σ-Δ, parallel interface
AD7763
OFFSET AND GAIN
CONTROL LOGIC
REGISTERS
I/O
© 2005 Analog Devices, Inc. All rights reserved.
DIFF
Figure 1.
V
IN–
V
IN+
RECONSTRUCTION
PROGRAMMABLE
MODULATOR
DECIMATION
FIR FILTER
MULTIBIT
ENGINE
Σ-Δ
AD7763
www.analog.com
AV
AV
AV
AV
DECAPA
DECAPB
R
AGND
V
DV
DGND
DRIVE
BIAS
DD1
DD2
DD3
DD4
DD

EVAL-AD7763EBZ Summary of contents

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FEATURES 120 dB dynamic range at 78 kHz output data rate 109 dB dynamic range at 625 kHz output data rate 112 dB SNR at 78 kHz output data rate 107 dB SNR at 625 kHz output data rate 625 ...

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AD7763 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Specifications..................................................................................... 3 Timing Specifications....................................................................... 5 Timing Diagrams.......................................................................... 6 Absolute Maximum Ratings............................................................ 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Terminology ...

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SPECIFICATIONS 2 DD1 DD DRIVE DD2 using on-chip amplifier with components as shown in Table 10, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Decimate × 256 Dynamic Range 2 ...

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AD7763 Parameter REFERENCE INPUT V Input Voltage REF V Input DC Leakage Current REF V Input Capacitance REF POWER DISSIPATION Total Power Dissipation Standby Mode POWER REQUIREMENTS AV (Modulator Supply) DD1 AV (General Supply) DD2 AV (Differential Amplifier Supply) DD3 ...

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TIMING SPECIFICATIONS 2 DD1 DD DRIVE DD2 Table 3. Parameter Limit MIN MAX f 1 MCLK 40 f 500 ICLK × t ...

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AD7763 TIMING DIAGRAMS FSO ( SCO ( DRDY ( SDO (O) D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 ...

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ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 4. Parameter Rating AV to GND −0 DD1 ( GND −0 DD2 DD3 DD4 DV ...

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AD7763 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DGND MCLKGND MCLK AV AGND2 AV AGND1 DECAPA REFGND V AGND4 AV AGND2 AV AV AGND2 Table 5. Pin Function Descriptions Pin No. Mnemonic DD1 4, 14, 15 DD2 ...

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Pin No. Mnemonic 17 R BIAS 37 RESET 3 MCLK 2 MCLKGND 36 SYNC 38 DRDY 39, 40, 45 SH2 ADR2:0 49 SCP 50 SDL 51 FSI 52 SDI 54 SDO 55 SCO 56 FSO 58 CDIV ...

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AD7763 TERMINOLOGY Signal-to-Noise Ratio (SNR) The ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist fre- quency, excluding harmonics and dc. The value for SNR is expressed ...

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TYPICAL PERFORMANCE CHARACTERISTICS 2 DD1 DD DRIVE DD2 are generated from 65536 samples using a 7-term Blackman-Harris window. 0 –50 –100 –150 –200 –250 0 5000 10000 15000 20000 FREQUENCY ...

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AD7763 0 –50 –100 –150 –200 –250 0 50000 100000 150000 200000 FREQUENCY (Hz) Figure 12. Normal Mode FFT, 100 kHz, −0.5 dB Input Tone, 32× Decimation 0 –50 –100 –150 –200 –250 0 50000 100000 150000 200000 FREQUENCY (Hz) ...

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CODE Figure 18. Normal Mode, 24-Bit Histogram, 256× Decimation 0.0010 +85 ° C 0.0005 +25 ° –40 ° C –0.0005 –0.0010 0 ...

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AD7763 THEORY OF OPERATION The AD7763 employs a Σ-Δ conversion technique to convert the analog input into an equivalent digital word. The modulator samples the input waveform and outputs an equivalent digital word to the digital filter at a rate ...

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AD7763 INTERFACE READING DATA USING THE SPI INTERFACE The timing diagram in Figure 2 shows how the AD7763 transmits its conversion results using the SPI-compatible serial interface. The data being read from the AD7763 is clocked out using the serial ...

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AD7763 Using the Address Pins ADR[2:0], all devices that share the serial bus are assigned binary addresses from 000 to 111 (depending on the number of devices in the share scheme). The address assigned to each device must not have ...

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Thus, if this bit is set to logic high, every device on the serial bus accepts the data written, regardless of the address bits. This feature is particularly attractive if, for example, four devices are being configured with the same ...

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AD7763 2 READING DATA USING THE I S INTERFACE The AD7763 has the capability of operating using an I interface. The interface is functional only for the output of stereo data and does not apply to writing to control registers, ...

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CLOCKING THE AD7763 The AD7763 requires an external, low jitter clock source. This signal is applied to the MCLK pin, and the MCLKGND pin is used to sense the ground from the clock source. An internal clock signal (ICLK) is ...

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AD7763 DRIVING THE AD7763 The AD7763 has an on-chip differential amplifier that operates with a supply voltage (AV ) from 3. 5.25 V. For a 4.096 V DD3 reference, the supply voltage must achieve ...

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Sampling Switch SS1 and Sampling Switch SS3 are driven by ICLK, whereas Sampling Switch SS2 and Sampling Switch SS4 are driven by ICLK . When ICLK is high, the analog input voltage is connected to CS1. On the falling edge ...

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AD7763 DECOUPLING AND LAYOUT RECOMMENDATIONS Due to the high performance nature of the AD7763, correct decoupling and layout techniques are required to obtain the performance as stated within this data sheet. Figure 35 shows a simplified connection diagram for the ...

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... The Design Tools section of the AD7763 product page on the Analog Devices website contains the Gerber files for the AD7763 evaluation board. These files should be used as a reference when designing any system using the AD7763. The location and orientation of some of the components ...

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AD7763 PROGRAMMABLE FIR FILTER As discussed in the Theory of Operation section, the third FIR filter on the AD7763 can be programmed by the user. The default coefficients that are loaded on reset are shown in Table 12. This gives ...

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DOWNLOADING A USER-DEFINED FILTER As discussed in the Programmable FIR Filter section, each of the filter coefficients is 27 bits in length: one sign bit and 26 magni- tude bits. To download coefficients for a user-specific FIR filter, a 32-bit ...

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AD7763 EXAMPLE FILTER DOWNLOAD The following is an example of downloading a short, user-defined filter with 24 taps. The frequency response is shown in Figure 38 –10 –20 –30 –40 –50 –60 –70 –80 0 100 200 300 ...

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REGISTERS The AD7763 has a number of user-programmable registers. The control registers are used to set the decimation rate, the filter configuration, the low power option, and the control of the differential amplifier. There are also digital gain, offset, and ...

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AD7763 STATUS REGISTER (READ ONLY) MSB PART 1 PART 0 DIE 2 DIE 1 DIE 0 Table 19. Bit Mnemonic Comment 15,14 PART[1:0] Part Number. These bits are constant for the AD7763 DIE[2:0] Die Number. These bits ...

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... COMPLIANT TO JEDEC STANDARDS MS-026-ACD-HD Figure 39. 64-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-64-2) Dimensions shown in millimeters Package Description 64-Lead Thin Quad Flat Package, Exposed Pad (TQFP_EP) 64-Lead Thin Quad Flat Package, Exposed Pad (TQFP_EP) Evaluation Board Rev Page 10.20 10.00 SQ EXPOSED 9 ...

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AD7763 NOTES Rev Page ...

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NOTES Rev Page AD7763 ...

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AD7763 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05476-0-10/05(0) Rev Page ...